公开(公告)号：DE69800792T2

公开(公告)日：2001-08-30

申请号：DE69800792

申请日：1998-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/72

Abstract: The JO parameter is coded on Q asterisk L bits with JO = JOQ-1.. JO0, Q and L are whole numbers. The method involves the following stages: - load a data bit NO, coded with Q asterisk L bits, the low weight bit of NO being equal to 1, into a register. Load into second and third registers (10,11) Q asterisk L zeros and load L zeros into a fourth register (60); - formation of a Q iteration loop indexed by (j) which varies from 0 to Q -1, which includes the two additional sub stages. Sub stage 2.1 form an iteration loop; - form an L iteration loop, indexed.by (I) which varies from O to L -1; - shift the contents of the fourth register (60) towards the right, this operation correspond to a division by 2 of the register contents; - test the bits resulting from this shift in a test circuit (63): if the control bit is 1; shift to the right the contents of the register (11) towards the right and load a 0 on the highest weight bit in this register. In a register (16) add bit by bit the contents of register (60) with zeros in an adder (64). The output of the adder (64) is connected to the input of register (60). Test with the second bit of low weight the output of the first register. Otherwise: shift to the right the contents of register (11), load with a 1 the high weight bit of the third register and in the register (16) add bit by bit the contents of the register (60) with the last L bits of the first register (12), in the adder (61). The first register (12) forms a register of L bits whose input and output are connected , and test with the second low weight bit the output of the first adder (61). Sub stage 2.2; - shift the contents of the whole of the first register (12)and produce, in a multiplier circuit (19), the multiplication of the contents of the register (12) by the contents of a fifth register (16), the latter having been filled with logic zeros if its size is greater than L; - shift the contents of the second register (10) and add the contents with the result of the multiplication, coded on Q asterisk L bits, in a second adder (30). Store in the second register (10) the Q asterisk L bits of high weight with the binary product produced by the second adder (31), and store the L bits of the lowest weight of these Q asterisk L bits in the fourth register (6).

公开(公告)号：DE69606273T2

公开(公告)日：2000-05-31

申请号：DE69606273

申请日：1996-11-27

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/72

公开(公告)号：DE69800792D1

公开(公告)日：2001-06-21

申请号：DE69800792

申请日：1998-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/72

Abstract: The JO parameter is coded on Q asterisk L bits with JO = JOQ-1.. JO0, Q and L are whole numbers. The method involves the following stages: - load a data bit NO, coded with Q asterisk L bits, the low weight bit of NO being equal to 1, into a register. Load into second and third registers (10,11) Q asterisk L zeros and load L zeros into a fourth register (60); - formation of a Q iteration loop indexed by (j) which varies from 0 to Q -1, which includes the two additional sub stages. Sub stage 2.1 form an iteration loop; - form an L iteration loop, indexed.by (I) which varies from O to L -1; - shift the contents of the fourth register (60) towards the right, this operation correspond to a division by 2 of the register contents; - test the bits resulting from this shift in a test circuit (63): if the control bit is 1; shift to the right the contents of the register (11) towards the right and load a 0 on the highest weight bit in this register. In a register (16) add bit by bit the contents of register (60) with zeros in an adder (64). The output of the adder (64) is connected to the input of register (60). Test with the second bit of low weight the output of the first register. Otherwise: shift to the right the contents of register (11), load with a 1 the high weight bit of the third register and in the register (16) add bit by bit the contents of the register (60) with the last L bits of the first register (12), in the adder (61). The first register (12) forms a register of L bits whose input and output are connected , and test with the second low weight bit the output of the first adder (61). Sub stage 2.2; - shift the contents of the whole of the first register (12)and produce, in a multiplier circuit (19), the multiplication of the contents of the register (12) by the contents of a fifth register (16), the latter having been filled with logic zeros if its size is greater than L; - shift the contents of the second register (10) and add the contents with the result of the multiplication, coded on Q asterisk L bits, in a second adder (30). Store in the second register (10) the Q asterisk L bits of high weight with the binary product produced by the second adder (31), and store the L bits of the lowest weight of these Q asterisk L bits in the fourth register (6).

公开(公告)号：FR2788616A1

公开(公告)日：2000-07-21

申请号：FR9900472

申请日：1999-01-15

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  MONIER GUY ,  LEPAREUX MARIE NOELLE

IPC: G06F7/52 ,  G06F7/72 ,  G06F11/10

Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.

公开(公告)号：DE69900127T2

公开(公告)日：2001-09-13

申请号：DE69900127

申请日：1999-03-23

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/52 ,  G06F7/535 ,  G06F7/72

Abstract: The result is produced by an iterative loop operation which includes: - whole division of the first data (M) by a high weight word from the second data (D); - a test to see if the result of the division corresponds to the result wanted; - modification of the first data by subtracting a data product, produced by multiplying the second data (D) by the result word produced in the preceding iteration.

公开(公告)号：DE69900127D1

公开(公告)日：2001-07-05

申请号：DE69900127

申请日：1999-03-23

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/52 ,  G06F7/535 ,  G06F7/72

Abstract: The result is produced by an iterative loop operation which includes: - whole division of the first data (M) by a high weight word from the second data (D); - a test to see if the result of the division corresponds to the result wanted; - modification of the first data by subtracting a data product, produced by multiplying the second data (D) by the result word produced in the preceding iteration.

公开(公告)号：FR2788616B1

公开(公告)日：2001-04-20

申请号：FR9900472

申请日：1999-01-15

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  MONIER GUY ,  LEPAREUX MARIE NOELLE

IPC: G06F7/52 ,  G06F7/72 ,  G06F11/10

Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.

公开(公告)号：DE69703085T2

公开(公告)日：2001-01-18

申请号：DE69703085

申请日：1997-12-19

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/52 ,  G06F7/72

Abstract: The processor (4b) has first and second multiplier circuits (19,20) and adder and multiplexer circuits. The multipliers have a serial input which receives n bits, a parallel input which receives k bits and a serial output that delivers n+k bits. The adder and multiplexer circuits permit addition of the data produced by the two multiplier circuits and other data coded on n bits. These circuits provide parallel multiplication to perform modular or non-modular arithmetic on binary data coded on n or more bits, allowing application of Montgomery's method for rapid encryption and decryption. Five registers are used to store the binary data before the arithmetic operations are performed.

公开(公告)号：DE69707717D1

公开(公告)日：2001-11-29

申请号：DE69707717

申请日：1997-01-09

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/52 ,  G06F7/72 ,  G09C1/00

Abstract: PCT No. PCT/FR97/00035 Sec. 371 Date Jul. 9, 1998 Sec. 102(e) Date Jul. 9, 1998 PCT Filed Jan. 9, 1997 PCT Pub. No. WO97/25668 PCT Pub. Date Jul. 17, 1997A modular arithmetic coprocessor designed to perform computations according to the Montgomery method includes a division circuit to perform integer divisions. The integer division circuit computes the division of a binary data element A encoded on n+Z +n (bits by a binary data element B encoded on n bits, A, B, n, n' and n'' being on-zero integers. For this function, the integer division circuit includes: a first n-bit register and a second n-bit register to contain the binary data element A and the result of the division, a third n-bit register to contain an intermediate result, a fourth n-bit register to contain the binary data element B, two subtraction circuits each having a first series input and a second series input and a series output, and a test circuit having an input and an output.

公开(公告)号：DE69703085D1

公开(公告)日：2000-10-19

申请号：DE69703085

申请日：1997-12-19

Applicant: ST MICROELECTRONICS SA

Inventor： MONIER GUY

IPC: G06F7/52 ,  G06F7/72

Abstract: The processor (4b) has first and second multiplier circuits (19,20) and adder and multiplexer circuits. The multipliers have a serial input which receives n bits, a parallel input which receives k bits and a serial output that delivers n+k bits. The adder and multiplexer circuits permit addition of the data produced by the two multiplier circuits and other data coded on n bits. These circuits provide parallel multiplication to perform modular or non-modular arithmetic on binary data coded on n or more bits, allowing application of Montgomery's method for rapid encryption and decryption. Five registers are used to store the binary data before the arithmetic operations are performed.