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    METHOD FOR SCRAMBLING CALCULATION WITH SECRET QUANTITY
    1.
    发明专利
    METHOD FOR SCRAMBLING CALCULATION WITH SECRET QUANTITY 审中-公开

    公开(公告)号：JP2003177668A

    公开(公告)日：2003-06-27

    申请号：JP2002259962

    申请日：2002-09-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE

    IPC: G09C1/00 ,  G06F7/38 ,  G06F7/72

    Abstract: PROBLEM TO BE SOLVED: To provide a method for scrambling a calculation involving at least one operation taking into account a secret quantity with less resources than heretofore, and to reduce or minimize the storage duration of a random quantity used for the scrambling or unnecessitate the storage of the random quantity. SOLUTION: In the method, at least one intermediary result takes into account at least one secret quantity, modifies the intermediary result with a random quantity, carries on the calculation with the modified result, and restores an expected result at the end of the calculation. COPYRIGHT: (C)2003,JPO

    VERIFICATION OF DATA READ IN MEMORY
    2.
    发明申请
    VERIFICATION OF DATA READ IN MEMORY 审中-公开
    数据在内存中的读取验证

    公开(公告)号：WO2009071791A2

    公开(公告)日：2009-06-11

    申请号：PCT/FR2008052073

    申请日：2008-11-18

    Applicant: ST MICROELECTRONICS SA ,  PROTON WORLD INT NV ,  ROMAIN FABRICE ,  MODAVE JEAN-LOUIS

    Inventor： ROMAIN FABRICE ,  MODAVE JEAN-LOUIS

    IPC: G06F21/55 ,  G06F21/60

    CPC classification number: G06F21/606 ,  G06F21/755

    Abstract: The invention relates to a method and a circuit for verifying data transferred between a circuit (21) and a processing unit (11), in which: the data originating from the circuit travels through a first temporary storage element (23) having a size representing an integer multiple of the size of data liable to be presented subsequently on a bus (27) of the processing unit; an address provided by the processing unit (11) destined for the circuit is stored temporarily in a second element (22); and the content of the first element is compared with a current data item (CDATA) originating from the circuit, at least when said data item corresponds to an address of a data item already present in this first element.

    Abstract translation: 本发明涉及用于验证在电路（21）和处理单元（11）之间传送的数据的方法和电路，其中：源自电路的数据通过第一临时存储元件（23） 在处理单元的总线（27）上易于呈现的数据的大小的整数倍; 由处理单元（11）提供给该电路的地址暂时存储在第二元件（22）中; 并且至少当所述数据项对应于已经存在于该第一元素中的数据项的地址时，将第一元素的内容与源自该电路的当前数据项（CDATA）进行比较。

    4.
    发明专利
    未知

    公开(公告)号：DE60023770T2

    公开(公告)日：2006-06-01

    申请号：DE60023770

    申请日：2000-02-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

    IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

    Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

    7.
    发明专利
    未知

    公开(公告)号：DE60207818D1

    公开(公告)日：2006-01-12

    申请号：DE60207818

    申请日：2002-02-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

    IPC: G09C1/00 ,  H04L9/06

    Abstract: A secured method of cryptographic computation to generate output data from input data and from a secret key includes a derived key scheduling step to provide a derived key from the secret key according to a known key scheduling operation. The method also includes a masking step, performed before the derived key scheduling step, to mask the secret key so that the derived scheduled key is different at each implementation of the method. The present method and component can be used in transfer type applications, such as bank type applications.

    8.
    发明专利
    未知

    公开(公告)号：DE60023770D1

    公开(公告)日：2005-12-15

    申请号：DE60023770

    申请日：2000-02-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

    IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

    Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

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