公开(公告)号：FR2843482A1

公开(公告)日：2004-02-13

申请号：FR0210195

申请日：2002-08-12

Applicant: ST MICROELECTRONICS SA

Inventor： PEYCHERAN STEPHANE ,  MORAGUES JEAN MICHEL ,  DUVAL BENJAMIN

IPC: G11C17/16 ,  G11C17/18

Abstract: The circuit comprises an anti-fuse transistor (100) whose drain, source and bulk (well) are connected together constituting one electrode, and whose gate is the other electrode. In the programming phase a higher potential (HT) is applied to the first electrode by the intermediary of an access transistor (110), and a reference potential, for example the ground potential, which is lower than the higher potential is applied to the gate. The circuit also comprises a second access transistor (120) connected between the gate of the anti-fuse transistor and the ground, a third access transistor (140) connected between the first electrode of the anti-fuse transistor and the ground, and a current source (130) connected between the gate of the anti-fuse transistor and a supply potential (VDD). The higher potential (HT) is, for example, 10.5 V for an anti-fuse transistor with the gate oxide layer of thickness 50 A. In the second embodiment, a branch comprising a second access transistor in series with the current source is connected between the source of the anti-fuse transistor and the supply potential (VDD). In the third embodiment, the current source is connected in series with the third access transistor, and a fourth access transistor is connected between the gate of the anti-fuse transistor and the supply potential (VDD). In the fourth embodiment, a branch with a third access transistor in series with the current source is connected between the gate of the anti-fuse transistor and the ground, and a fourth access transistor is connected between the source of the anti-fuse transistor and the supply potential (VDD). The method (claimed) is implemented by the circuit (claimed).