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    METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON
    1.
    发明申请
    METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON 审中-公开
    用于本地时钟产生的方法和电路以及包括它的智能卡

    公开(公告)号：WO2007042928A2

    公开(公告)日：2007-04-19

    申请号：PCT/IB2006002860

    申请日：2006-10-06

    Applicant: AXALTO SA ,  ST MICROELECTRONICS SA ,  LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

    Inventor： LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

    IPC: G06F1/04 ,  H03L7/197

    CPC classification number: G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

    Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal f(0) to f(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal f(0) to j(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal f(0) to f(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

    Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号f（0）至f（2-i-1）被提供有基本的时间步长。 在接收到的比特流内测量与比特持续时间相对应的时间步长的合理数量。 振荡器信号f（0）至j（2≤I-1）被变换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号f（0）至f （2 i），两个连续的有效边缘被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。

    DETECTEUR DE PICS PARASITES DANS L'ALIMENTATION D'UN CIRCUIT INTEGRE
    3.
    发明专利
    DETECTEUR DE PICS PARASITES DANS L'ALIMENTATION D'UN CIRCUIT INTEGRE 未知

    公开(公告)号：FR2895115A1

    公开(公告)日：2007-06-22

    申请号：FR0553962

    申请日：2005-12-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： MALHERBE ALEXANDRE ,  DUVAL BENJAMIN

    IPC: G06K19/073 ,  G06F12/14 ,  G11C5/14

    Abstract: L'invention concerne un circuit de détection de pics parasites sur l'alimentation d'un circuit électronique, comportant au moins un premier transistor (MP51) dont la borne de commande est reliée à une borne (52) d'application d'un premier potentiel d'une tension d'alimentation (Vcc) du circuit et dont une première borne de conduction est reliée à une borne (52) d'application d'un deuxième potentiel (Vcc) par l'intermédiaire d'au moins un premier élément résistif (R1), la deuxième borne de conduction du premier transistor fournissant le résultat (Vd) de la détection.

    Reference current generator for low voltage integrated circuit, uses P and N type transistors one of which operates in saturated mode
    4.
    发明专利
    Reference current generator for low voltage integrated circuit, uses P and N type transistors one of which operates in saturated mode 未知

    公开(公告)号：FR2829248A1

    公开(公告)日：2003-03-07

    申请号：FR0111356

    申请日：2001-09-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN

    IPC: G05F3/24 ,  G05F3/26

    Abstract: The current generator has a current source (SI) having a first pole to which is applied a voltage (VDD) and a second pole connected to a resistance (R2). A reference voltage (VSS) is applied to the drain of a transistor (T7). The grid and source of an N type transistor (T11) are respectively connected to the grid and source of a transistor (T8).. Reference current (I8) generator which includes: (a) a first P type transistor (T7) whose source is connected to a first pole of a resistance (R2) and whose grid is connected to a second pole of the resistance (R2). The current reference (I8) passing through the resistance (R2) varies as a function of the voltage level of the first transistor, and; a second N type transistor (T8) whose drain, grid and source are respectively connected to the first and second pole of resistance (R2), and to the drain of transistor (T7). The transistor (T8) operates in saturated mode.

    CIRCUIT ELECTRONIQUE EQUIPE POUR EVALUER SA TEMPERATURE, PROCEDE D'EVALUATION DE TEMPERATURE, ET APPLICATIONS
    5.
    发明专利
    CIRCUIT ELECTRONIQUE EQUIPE POUR EVALUER SA TEMPERATURE, PROCEDE D'EVALUATION DE TEMPERATURE, ET APPLICATIONS 未知

    公开(公告)号：FR2874259A1

    公开(公告)日：2006-02-17

    申请号：FR0408853

    申请日：2004-08-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN ,  POMET ALAIN

    IPC: G01K7/00 ,  G01R31/28

    Abstract: L'invention concerne notamment un circuit électronique (CE) doté d'un oscillateur (OSC_1) délivrant un signal (S1) de fréquence (F1) variable avec la température (Tc) de ce circuit, et recevant ou délivrant un signal (S2) de fréquence (F2) fixe et connue.Ce circuit comprend un module de mesure (MSR) délivrant un signal de mesure (Φ1) représentatif de la fréquence variable (F1) évaluée sur la base du signal (S2) à fréquence fixe pris comme référence ou étalon, et un module de conversion (CVRS) appliquant au signal de mesure (Φ1) une fonction de transfert inverse (u-1, v-1, w-1) de la loi de variation en fonction de la température de la fréquence du premier signal (S1), pour produire un signal de sortie (Θc) représentatif de la température (Tc) du circuit.

    Method for programming memory cells by breaking down antifuse elements
    6.
    发明专利
    Method for programming memory cells by breaking down antifuse elements 未知

    公开(公告)号：FR2838233A1

    公开(公告)日：2003-10-10

    申请号：FR0204184

    申请日：2002-04-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN ,  MARINET FABRICE

    IPC: G11C17/18 ,  G11C17/16 ,  G11C11/34

    Abstract: The method for programming a row of antifuse memory cells (SEL1-SELN) connected in parallel comprises a step of breakdown of at least N antifuse elements (AF1-AFN) contained in the memory cells, which becomes conducting by breakdown. The breakdown of an antifuse element is carried out by applying a breakdown voltage (Vhv) onto the anode of the antifuse element. The antifuse elements are broken down sequentially in groups of P elements, where P is less than N and at least equal to 1. The antifuse elements of the same group receives the breakdown voltage simultaneously, and the breakdown of the next group of the antifuse elements follows the breakdown of the preceding group of the antifuse elements. The antifuse elements are broken down individually one after another when P = 1. The value of P is chosen so that the total time (TP) of the breakdown of N antifuse elements is optimal. The number P is not constant during the programming of the row of memory cells. The method comprises a step of detecting the breakdown of the antifuse elements manifested in a voltage on the cathode of the antifuse elements higher than a determined threshold (Vref). The cathode voltage and the reference voltage are input to a comparator (CMP), which delivers a signal (SHIFT) to the control input of a shift register (SREG) comprising N cells in cascade (C1 - CN) for controlling switches in pairs: SWA1 and SWB1, ..., SWAN and SWBN. The antifuse memory in the form of an integrated circuit implements the method as claimed, and comprises means for sequentially applying the breakdown voltage to the groups of antifuse elements.

    An electronic circuit for detecting a supply potential as having a sufficient value after switching on, for use in integrated circuit devices such as chip cards
    7.
    发明专利
    An electronic circuit for detecting a supply potential as having a sufficient value after switching on, for use in integrated circuit devices such as chip cards 未知

    公开(公告)号：FR2844118A1

    公开(公告)日：2004-03-05

    申请号：FR0210702

    申请日：2002-08-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN ,  MARINET FABRICE

    IPC: H03K17/22

    Abstract: The circuit for detecting a supply potential (VDD,VINT) comprises basically two branches: the first branch with two resistors (R1,R2) and a bipolar transistor (TB1) producing the first image potential (VP), and the second branch with a resistor (R3) and a bipolar transistor (TB2) producing the second image potential (VM); and a comparator (COMP) producing a blocking or holding signal (POR) which is in a first logic state (active) when the first image potential (VP) is below the second iamge potential (VM), and in a second logic state (inactive) otherwise. The first image potential (VP) increases slowly with the supply potential, and the second image potential (VM) increases rapidly with the supply potential. The two image potentials are equal when the supply potential is equal to a characteristic constant of the circuit. Each bipolar transistor (TB1,TB2) has its base and its collector connected together to the ground. The two resistances (R2,R3) are equal. In a variant of the circuit (dotted line), a voltage divider bridge with two resistors (R4,R5) receives the supply potential (VDD) and produces a measure potential (VINT) which is proportional to the supply potential, and a capacitor (C) is connected in parallel with the two branches.

    Method and circuit for programming an anti-fuse transistor for use in electronic circuits, the transistor has drain, source and bulk connected together and gate as other electrode
    8.
    发明专利
    Method and circuit for programming an anti-fuse transistor for use in electronic circuits, the transistor has drain, source and bulk connected together and gate as other electrode 未知

    公开(公告)号：FR2843482A1

    公开(公告)日：2004-02-13

    申请号：FR0210195

    申请日：2002-08-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： PEYCHERAN STEPHANE ,  MORAGUES JEAN MICHEL ,  DUVAL BENJAMIN

    IPC: G11C17/16 ,  G11C17/18

    Abstract: The circuit comprises an anti-fuse transistor (100) whose drain, source and bulk (well) are connected together constituting one electrode, and whose gate is the other electrode. In the programming phase a higher potential (HT) is applied to the first electrode by the intermediary of an access transistor (110), and a reference potential, for example the ground potential, which is lower than the higher potential is applied to the gate. The circuit also comprises a second access transistor (120) connected between the gate of the anti-fuse transistor and the ground, a third access transistor (140) connected between the first electrode of the anti-fuse transistor and the ground, and a current source (130) connected between the gate of the anti-fuse transistor and a supply potential (VDD). The higher potential (HT) is, for example, 10.5 V for an anti-fuse transistor with the gate oxide layer of thickness 50 A. In the second embodiment, a branch comprising a second access transistor in series with the current source is connected between the source of the anti-fuse transistor and the supply potential (VDD). In the third embodiment, the current source is connected in series with the third access transistor, and a fourth access transistor is connected between the gate of the anti-fuse transistor and the supply potential (VDD). In the fourth embodiment, a branch with a third access transistor in series with the current source is connected between the gate of the anti-fuse transistor and the ground, and a fourth access transistor is connected between the source of the anti-fuse transistor and the supply potential (VDD). The method (claimed) is implemented by the circuit (claimed).

    10.
    发明专利
    未知

    公开(公告)号：DE602006009447D1

    公开(公告)日：2009-11-12

    申请号：DE602006009447

    申请日：2006-07-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUVAL BENJAMIN ,  POMET ALAIN

    IPC: G06F13/40

    Abstract: The peripheral has an interface circuit with a detection circuit (DCT) detecting the presence or absence of pull-down resistors of a master device (H) e.g. computer. The circuit (DCT) is connected to positive and negative data terminals (D+, D-) of a universal serial bus (USB) port of the peripheral. The peripheral establishes a communication with the device (H) via the port, if the circuit (DCT) detects the resistors. The circuit (DCT) verifies if voltages applied to the data terminals exceed 0.8 volts, if DC voltages (Vg+, Vg-, Vg) provided by a generator (VGEN) is less than 0.8 volts.

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