公开(公告)号：FR2813145B1

公开(公告)日：2002-11-29

申请号：FR0010727

申请日：2000-08-18

Applicant: ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  PELLOIE JEAN LUC

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/30 ,  H01L29/94 ,  H01L29/12

Abstract: The capacitor manufacture method for several levels of metallization has a step of formation at an inter track isolating level (3) two electrodes (50, 70) and a dielectric layer (60) with a conductor slice (51). At the upper track level (8) two conductor pads (80, 87) are formed contacting the upper electrode and the conductor slice.

公开(公告)号：FR2813145A1

公开(公告)日：2002-02-22

申请号：FR0010727

申请日：2000-08-18

Applicant: ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  PELLOIE JEAN LUC

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/30 ,  H01L29/94 ,  H01L29/12

Abstract: The capacitor manufacture method for several levels of metallization has a step of formation at an inter track isolating level (3) two electrodes (50, 70) and a dielectric layer (60) with a conductor slice (51). At the upper track level (8) two conductor pads (80, 87) are formed contacting the upper electrode and the conductor slice.