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公开(公告)号：FR2897174A1
公开(公告)日：2007-08-10
申请号：FR0601091
申请日：2006-02-08
Applicant: ST MICROELECTRONICS SA
Inventor： AYRIGNAC RENAUD , ROBERT XAVIER
Abstract: L'invention concerne un processeur (&muP) comprenant une unité de traitement (CPU) et une interface de déboguage (OCE) susceptible d'être connectée à un émulateur externe (H) pour déboguer un programme exécuté par le processeur, l'interface de déboguage comprenant des ressources internes (ER0-ERn) au moins partiellement accessibles à l'émulateur externe. Selon l'invention, l'interface de déboguage (OCE) comprend un circuit de sélection pour sélectionner une ressource interne (ER0-ERn) de l'interface de déboguage, en fonction d'une référence (ADR) fournie par l'unité de traitement (CPU), et des moyens d'accès pour transférer une donnée entre la ressource sélectionnée et un champ de donnée (D) accessible par l'unité de traitement.
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公开(公告)号：DE60228766D1
公开(公告)日：2008-10-16
申请号：DE60228766
申请日：2002-11-21
Applicant: ST MICROELECTRONICS SA
Inventor： ROBERT XAVIER
Abstract: The invention concerns a monitoring device ( 18 ) integrated to a microprocessor chip ( 12 ) executing a series of instructions comprising: device ( 26 ) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer ( 28 ) divided into several blocks (A, B, C, D, E) each of which is designed to store only messages of one of the types capable of being produced simultaneously, the size of each block depending on the maximum frequency at which the messages can be stored, and device ( 26 ) for, each time one or more messages are simultaneously stored in the blocks (A, B, C, D, E) of the buffer ( 28 ), storing in a predetermined block (F) of the buffer a coded value representing said block(s) of the buffer.
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公开(公告)号：FR2897174B1
公开(公告)日：2008-04-18
申请号：FR0601091
申请日：2006-02-08
Applicant: ST MICROELECTRONICS SA
Inventor： AYRIGNAC RENAUD , ROBERT XAVIER
Abstract: The processor has a CPU, and a debugging interface (OCE) connected to an external emulator (H) for debugging a program executed by the processor. The interface has internal registers (ER0-ERn) accessible to the emulator, and a selection circuit for selecting registers based on a reference provided by the CPU. A data bus transfers data between the selected register and a data field accessible by the CPU. An independent claim is also included for a method for accessing internal resources by a CPU of a processor.
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公开(公告)号：DE60222187D1
公开(公告)日：2007-10-11
申请号：DE60222187
申请日：2002-11-14
Applicant: ST MICROELECTRONICS SA
Inventor： ROBERT CATHERINE , ROBERT XAVIER , BARBIERO JEHAN-PHILIPPE
IPC: G06F11/28 , G06F11/267 , G06F11/30
Abstract: A method for the transmission of digital messages by the output terminals of a monitoring circuit which is integrated into a microprocessor, the digital messages being representative of first specific events which are dependent on the execution of a series of instructions by the microprocessor. The method includes transmitting the following signals to the monitoring circuit by dedicated access points, namely (i) a request signal for the sending of a message that is associated with a specific event from second specific events which are independent of the execution of the series of instructions by the microprocessor and (ii) a signal comprising characteristic data which are associated with the aforementioned specific event; forcing the monitoring circuit to read the request message and, if the resource management conditions are fulfilled, sending an acknowledgement message and storing said characteristic data signal and transmitting a digital message which is representative of the stored characteristic data signal.
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