公开(公告)号：JP2002198945A

公开(公告)日：2002-07-12

申请号：JP2001363669

申请日：2001-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  TARAYRE PIERRE

IPC: H04L7/04 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide a method for transmitting data between two devices (D1, D2) which can restrain a clock line to an electric potential representing a logic value B opposite to a logic value A respectively using a clock line (CK) maintained at the default value of the logic value A and at least one data line (DT). SOLUTION: By the method of this invention, both devices restrain the clock line to B when the data is transmitted, the device to which the data is transmitted doesn't release the clock line when the device doesn't end reading out the data, and the device which transmits the data maintains the data on the data line at least until when the clock line is released by the device to which the data is transmitted. This method is especially applied to the communication between a microcomputer and a microprocessor.

公开(公告)号：FR2817432B1

公开(公告)日：2003-01-24

申请号：FR0015387

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  TARAYRE PIERRE

IPC: H04L7/04 ,  G06F13/42 ,  H04L29/08 ,  G06F15/163

Abstract: Two devices (D1,D2) may transmit data using clock thread (CK) and at least a data thread (DT). The clock thread is maintained by default to a logical value A that may be converted to an electric potential representing a logical value B inverse of A. The two devices may convert B to the CK at the time of data transmission. A target device to which the data is sent does not loose the CK since it does not read the data. The data-sending device maintains it until the CK is released by the device to which data is targeted. Independent claims are included for: (a) a data transmission-reception device (b) a synchronous data transmission device (c) an interface circuit for data transmission in master-slave configuration

公开(公告)号：FR2817432A1

公开(公告)日：2002-05-31

申请号：FR0015387

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  TARAYRE PIERRE

IPC: H04L7/04 ,  G06F13/42 ,  H04L29/08 ,  G06F15/163

Abstract: Two devices (D1,D2) may transmit data using clock thread (CK) and at least a data thread (DT). The clock thread is maintained by default to a logical value A that may be converted to an electric potential representing a logical value B inverse of A. The two devices may convert B to the CK at the time of data transmission. A target device to which the data is sent does not loose the CK since it does not read the data. The data-sending device maintains it until the CK is released by the device to which data is targeted. Independent claims are included for: (a) a data transmission-reception device (b) a synchronous data transmission device (c) an interface circuit for data transmission in master-slave configuration