公开(公告)号：JP2001256116A

公开(公告)日：2001-09-21

申请号：JP2000382738

申请日：2000-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/34

Abstract: PROBLEM TO BE SOLVED: To safely transfer data in a programmable circuit (CP) provided with at least one control unit (UC), a read-only memory(ROM1) provided with transfer data, a writable memory(RAM1) and a data bus(DBUS) connected between the read-only memory(ROM1) and the writable memory (RAM1). SOLUTION: The secret data element of N-bytes to be transferred is shifted by a byte unit on the data bus(DBUS), the respective bytes are shifted on the data bus(DBUS) at least once and the bytes are shifted in a different order for each transfer of the same data element. When a loading indicator (ZR) takes a prescribed value (IN), the transfer of the secret data element is completed.

公开(公告)号：JP2001265713A

公开(公告)日：2001-09-28

申请号：JP2000382737

申请日：2000-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F7/58 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/10

Abstract: PROBLEM TO BE SOLVED: To provide a safe transfer method for data for a programmable circuit, which is provided with a control unit, a read only memory(ROM) having data to be transferred, a writable memory and a data bus for connecting the ROM and the writable memory, for controlling the data bus with the control unit. SOLUTION: The secret data element of N bits to be transferred is transited through the data bus for the unit of byte and each of bytes is transited through the data bus just once. Further, the byte is transferred according to a transfer rule having at least one parameter selected at random by the control unit before transferring each of secret data elements.

公开(公告)号：DE602007012805D1

公开(公告)日：2011-04-14

申请号：DE602007012805

申请日：2007-08-29

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: G06F7/72

公开(公告)号：DE602004029536D1

公开(公告)日：2010-11-25

申请号：DE602004029536

申请日：2004-08-27

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK ,  TOMEI AMBROISE

IPC: G06F7/58 ,  G06F9/30

公开(公告)号：DE602005022039D1

公开(公告)日：2010-08-12

申请号：DE602005022039

申请日：2005-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/06

公开(公告)号：DE602005017550D1

公开(公告)日：2009-12-24

申请号：DE602005017550

申请日：2005-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/06

Abstract: The method involves executing an algorithm with a valid data between several executions of same algorithm with an invalid data corresponding to a combination of the valid data with predetermined masks. The masks are selected so that result of application of the algorithm with same key is different for one bit from result of application of the algorithm to the valid data. An independent claim is also included for a processor for executing an encryption algorithm.

公开(公告)号：DE602004015029D1

公开(公告)日：2008-08-28

申请号：DE602004015029

申请日：2004-08-27

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK ,  TOMEI AMBROISE

IPC: G06F7/58 ,  H03K3/84 ,  G09C1/00

Abstract: The state of an output bit is conditioned to respective states of the bits of the initial flow examined by multibit words of identical lengths. The state of the current output bit is conditioned to the state of previous output bit, upon occurrence of word of bits of identical states. An independent claim is also included for bitflow normalization circuit.

公开(公告)号：DE60034921D1

公开(公告)日：2007-07-05

申请号：DE60034921

申请日：2000-12-06

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F7/58 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/10

Abstract: The secure data transfer operates in a programmable circuit containing a controller (UC), ROM and RAM, connected by a data bus (DBUS). N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, using a transfer rule that has a parameter chosen at random before each transfer, using a random number generator (GA).

公开(公告)号：FR2888350A1

公开(公告)日：2007-01-12

申请号：FR0552046

申请日：2005-07-05

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE YVAN

IPC: G06F7/58 ,  H03M7/40

Abstract: L'invention concerne un procédé de détermination de l'entropie d'une source de bruit (2) fournissant un flux de bits (BS), un procédé et dispositif de génération d'un flux de bits consistant à paralléliser le flux de bits pour obtenir des premiers mots sur un premier nombre (n1) de bits, appliquer aux mots successifs une fonction (2) de compression, et évaluer (7) un deuxième nombre (n2) de bits sur lequel ladite fonction de compression fournit ses résultats, le deuxième nombre représentant le nombre de bits utiles dans les premiers mots.

公开(公告)号：DE602004001293D1

公开(公告)日：2006-08-03

申请号：DE602004001293

申请日：2004-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F1/00 ,  G06F21/52 ,  G06F21/55

Abstract: The number of occurrences of operation during program execution are incremented and memorized, by comparing each operation with pre-established list. Number of occurrences are compared with previously stored ranges assigned to each operation at the end of execution. The ranges are determined by analyzing possible statistics deviations of the number of occurrences with respect to program execution. An independent claim is also included for processor for executing program.