公开(公告)号：JP2009260972A

公开(公告)日：2009-11-05

申请号：JP2009102195

申请日：2009-04-20

Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー

Inventor： TOUZARD OLIVIER ,  TOURNIER VERONIQUE

IPC: H03G3/10 ,  H03F3/45

CPC classification number: H03G1/0023 ,  H03F3/19 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2203/45392

Abstract: PROBLEM TO BE SOLVED: To provide a variable gain amplifier capable of reducing device current consumption and area by extremely decreasing the number of components through which RF signal must pass. SOLUTION: The variable gain amplifier comprises: an input node; a variable current source coupled to the input node; first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node via a capacitor. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可以通过极大地减少RF信号必须通过的分量的数量来减少器件电流消耗和面积的可变增益放大器。 解决方案：可变增益放大器包括：输入节点; 耦合到所述输入节点的可变电流源; 第一和第二分支并联耦合在第一电源端子和可变电流源之间，第一和第二分支限定一个差分对，其布置为由第一和第二差分增益信号控制，并具有第一和第二输出端子，输出之一 端子，包括可变增益放大器的输出节点; 以及具有耦合到所述第一和第二输出端子的中间节点的分压器，其中所述中间节点还经由电容器耦合到所述输入节点。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：DE69831202T2

公开(公告)日：2006-06-22

申请号：DE69831202

申请日：1998-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： BONHOURE BRUNO ,  TOURNIER VERONIQUE

IPC: H01L23/522 ,  H01L27/04 ,  H01L21/822

Abstract: An intermetallic capacitor is produced in a multilayer IC having five or more metallization levels by leaving, at each side of the capacitor, a level which is distinct from the substrate and the last metallization level and which is biased at the substrate potential. An Independent claim is also included for an intermetallic capacitor (C) formed in a multilayer IC having five or more metallization levels on a p-type substrate (21), in which the levels (23, 25), which define the outer portions of the capacitor, are separated by a polarizable level portion (22, 26) from the substrate (21) and the last metallization level (27), respectively.

公开(公告)号：DE69831202D1

公开(公告)日：2005-09-22

申请号：DE69831202

申请日：1998-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： BONHOURE BRUNO ,  TOURNIER VERONIQUE

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/522

Abstract: An intermetallic capacitor is produced in a multilayer IC having five or more metallization levels by leaving, at each side of the capacitor, a level which is distinct from the substrate and the last metallization level and which is biased at the substrate potential. An Independent claim is also included for an intermetallic capacitor (C) formed in a multilayer IC having five or more metallization levels on a p-type substrate (21), in which the levels (23, 25), which define the outer portions of the capacitor, are separated by a polarizable level portion (22, 26) from the substrate (21) and the last metallization level (27), respectively.