公开(公告)号：DE69831202T2

公开(公告)日：2006-06-22

申请号：DE69831202

申请日：1998-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： BONHOURE BRUNO ,  TOURNIER VERONIQUE

IPC: H01L23/522 ,  H01L27/04 ,  H01L21/822

Abstract: An intermetallic capacitor is produced in a multilayer IC having five or more metallization levels by leaving, at each side of the capacitor, a level which is distinct from the substrate and the last metallization level and which is biased at the substrate potential. An Independent claim is also included for an intermetallic capacitor (C) formed in a multilayer IC having five or more metallization levels on a p-type substrate (21), in which the levels (23, 25), which define the outer portions of the capacitor, are separated by a polarizable level portion (22, 26) from the substrate (21) and the last metallization level (27), respectively.

公开(公告)号：DE69831202D1

公开(公告)日：2005-09-22

申请号：DE69831202

申请日：1998-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： BONHOURE BRUNO ,  TOURNIER VERONIQUE

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/522

Abstract: An intermetallic capacitor is produced in a multilayer IC having five or more metallization levels by leaving, at each side of the capacitor, a level which is distinct from the substrate and the last metallization level and which is biased at the substrate potential. An Independent claim is also included for an intermetallic capacitor (C) formed in a multilayer IC having five or more metallization levels on a p-type substrate (21), in which the levels (23, 25), which define the outer portions of the capacitor, are separated by a polarizable level portion (22, 26) from the substrate (21) and the last metallization level (27), respectively.

公开(公告)号：DE69623681D1

公开(公告)日：2002-10-24

申请号：DE69623681

申请日：1996-04-09

Applicant: ST MICROELECTRONICS SA

Inventor： DELL OVA FRANCIS ,  BONHOURE BRUNO ,  PAILLARDET FREDERIC

IPC: H03F1/56 ,  G05F3/26 ,  G11B7/00 ,  H03F3/08 ,  H03F3/34 ,  H03F3/345 ,  H03F3/347

Abstract: The amplifier includes a MOS transistor with its drain connected to an input terminal (A) which receives the current (I) to be amplified. The transistor gate (MN1) is connected to earth (GND) via a dc current source (14) which delivers a current I. A cascode transistor (MP1) is connected to the gate and drain of the first transistor. A constant voltage (Vc) is applied to the gate of the second transistor, while a second current source (16) delivers a current 2I to its source. A third transistor (MN2) is connected with its source and drain in parallel with the first transistor (MN1). The current collected at its output is amplified by a factor n which is determined by the surface ratio of the two transistors.