公开(公告)号：FR2815197B1

公开(公告)日：2003-01-03

申请号：FR0012826

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SA

Inventor： HUGUES JEAN FRANCOIS ,  VIVET PASCAL

IPC: G06F9/38 ,  G06F11/16 ,  H03K19/003 ,  H03K21/40 ,  H03K23/58

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

公开(公告)号：FR2827443B1

公开(公告)日：2004-03-26

申请号：FR0109190

申请日：2001-07-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  HUGUES JEAN FRANCOIS ,  FERRANT RICHARD

IPC: H03K19/003 ,  H03K19/007

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

公开(公告)号：FR2795870A1

公开(公告)日：2001-01-05

申请号：FR9908488

申请日：1999-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL ,  VINCENT EMMANUEL ,  HUGUES JEAN FRANCOIS

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/525

Abstract: The semiconductor circuit (1) comprises electronic components or elements selectively connected and implemented at several levels, where at least two components or elements are connected to two respective portions of strip conductors (6,8; 7,9) belonging to the same level of metallisation (2); the two portions have adjacent parts situated in a zone (12,14) above which the circuit is free from electronic components or strip conductors. The circuit configuration is altered by making wells (15) in marked locations above zones (12,14) to expose the adjacent parts of strip conductors and to deposit a connection material (18,19) at the bottom of wells to electrically connect the portions of strip conductors and consequently the electronic components or elements. The adjacent parts of strip conductors are their extremities separated by a spacing which is at most equal to the width or thickness. At least one of electronic components is connected to another strip conductor (3) having a part situated in a marked zone above which the circuit is free from electronic components or strip conductors, where another well (17) is made to expose the part of strip conductor and to section the part in order to disconnect the components connected on two sides of sectioning (20). The making of wells (15,17), the deposition of connection material (18,19), the sectioning (20) and oxide deposition (21) are carried out by use of focused ion beam (FIB) technology.

公开(公告)号：FR2827443A1

公开(公告)日：2003-01-17

申请号：FR0109190

申请日：2001-07-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  HUGUES JEAN FRANCOIS ,  FERRANT RICHARD

IPC: H03K19/003 ,  H03K19/007

Abstract: The protection circuit receives an initial clock signal and transmits at least one, in particular three or four, resultant clock signals to a downstream circuit. The protection circuit comprises an input circuit receiving the input clock signal and generating two intermediate clock signals which are images of the initial clock signal, and a recombination circuit which delivers the resultant clock signals which are the images of the intermediate clock signals if the intermediate clock signals are identical, or inactive, that is corresponding to a high impedance, if the intermediate signals are different, as in an event causing a peak in current or voltage. The input circuit comprises two buffers, preferentially distanced in the circuit design, whose inputs are connected together to the circuit input, and whose outputs deliver the intermediate clock signals . The recombination circuit is specified in three embodiments, and comprises complex and simple inverter circuits. In the first embodiment, it comprises three complex inverter circuits, where the first complex inverter comprises two p-type and two n-type transistors connected in series between a supply voltage terminal and a ground; the gates of p-type and n-type transistors in pairs are connected to two inputs of the complex inverter. In the second embodiment, the recombination circuit comprises one complex inverter and three simple inverters; the simple inverter comprises a pair of transistors, p-type and n-type, connected in series between a supply voltage terminal and a ground; the gates of transistors are connected together to the inverter input; the recombination circuit delivers four resultant clock signals. In the third embodiment, the recombination circuit comprises two complex inverters and two simple inverters, and delivers four resultant clock signals. A clock circuit for an integrated circuit as claimed comprises the protection circuit, where the protection circuit is connected between the circuit input utilizing the clock signal and a part of a branch of the clock circuit.

公开(公告)号：FR2815197A1

公开(公告)日：2002-04-12

申请号：FR0012826

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SA

Inventor： HUGUES JEAN FRANCOIS ,  VIVET PASCAL

IPC: G06F9/38 ,  G06F11/16 ,  H03K19/003 ,  H03K21/40 ,  H03K23/58

Abstract: The asynchronous circuit with execution mode of instructions of micro-pipeline type comprises one or more logic states (E0,1,E2), where each stage comprises a computing logic block (1), two information-storage circuits or latches (2A,2B) whose inputs are connected to the output of the logic block, a control unit (3) delivering: the data-acquisition signals (Lt,Ltr) to the control inputs of latches, a signal (Ain) to a control unit of the preceding stage, and a signal (Rout) to a control unit of the next stage by the intermediary of delay circuits (4,7,8); and a comparator (6) whose inputs are connected to the outputs of latches and whose output signal (ALEA/NO-ALEA) is in two states, in the first state (NO-ALEA) when the two compared signals are identical and there is no induced error, and in the second state (ALEA) when the two signals are different and there is an induced error. The latches (2A,2B) are bistables. The control unit (3) contains circuits for delaying the first acquisition signal (Lt), which are in the form of a chain of inverters, or an RC circuit. The first delay route (9) comprises a delay circuit (8) introducing a delay (2 asterisk DL) which is two times greater than the pulse length of an induced error. The method for detecting and correcting an induced error in the asynchronous circuit includes the storage of the state of signal (Din) in latches (2A,2B), where the storage in the second laltch is with a delay of length (DL) which is greater than the pulse length of an induced error, and the comparison of the stored signals for the delivery of the two-state signal (ALEA/NO-ALEA). In the case of the first stage (NO-ALEA) the control unit (3) delivers the signal (Rout) without delay to the next stage; in the case of the second state (ALEA), the state of signal (Din) is stored for the second time in the first latch after another delay of length (DL), and the control unit delivers the signal (Rout) to the next stage with a delay of length (2 asterisk DL). In the method for detecting multiple induced errors the steps of storage and comparison are repeated in a loop unit an induced error is detected, and then the signal (Rout) is delivered with a delay of length equal to: (number of detected induced errors) asterisk 2 asterisk DL.