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    Dynamic read only memory test by cache reading , use Non-Or-Exclusive or Or-Exclusive with Non-Or-Exclusive logic circuits to check states of cache type temporary memory elements
    2.
    发明专利
    Dynamic read only memory test by cache reading , use Non-Or-Exclusive or Or-Exclusive with Non-Or-Exclusive logic circuits to check states of cache type temporary memory elements 未知

    公开(公告)号：FR2817997A1

    公开(公告)日：2002-06-14

    申请号：FR0016029

    申请日：2000-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  WADSWORTH ROB

    IPC: G11C29/38 ,  G11C7/24 ,  G01R31/317

    Abstract: Has logic circuit (40') of NON-OR-EXCLUSIVE type with temporary memory elements (10,20). Respective outputs of all columns of logic circuits are connected to a result line (MATCH) pre-loaded to first state. A logic circuit (40) executes an OR-EXCLUSIVE function and NON-OR-EXCLUSIVE function for states contained in temporary memory elements. The respective results of logic combinations are used to maintain or not pre-loaded state on complementary input-output lines of column. Volatile memory circuit having a number of memory cells (3) in a matrix network, and associated with each column of the network is at least a pair of temporary memory elements (10,20) independently controlled, one from the other. Associated with each pair of temporary memory elements is a logic circuit (40,40') dedicated to memory circuit testing and combing the respective states of the temporary memory elements. The logic circuits are activated by a control signal (TEST') for switching to test mode. Independent Claims are included for - the test method.

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