中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.027 seconds)

    4.
    发明专利
    未知

    公开(公告)号：DE60217286D1

    公开(公告)日：2007-02-15

    申请号：DE60217286

    申请日：2002-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： URZI IGNAZIO ,  FIENI MASSIMILIANO ,  PISASALE SALVATORE

    IPC: G06F1/12 ,  G06F5/06

    Abstract: A converter circuit for performing transfer of control logic signals between one first device (2) and one second device (3) coming under an interconnection bus, the first device (2) operating the frequency of a first clock signal (clock_1) and the second device (3) operating at the frequency of a second clock signal (clock_2). The clock frequencies in question may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The control signals comprise: an access-request signal (req_1, req_2) to be transferred from the first device (2) to the second device (3) ; a grant signal (gnt_1, gnt_2) to be transferred from the second device (3) to the first device (2); and a response-to-request signal (r_req_1, r_req_2) to be transferred from the second device (3) to the first device (2). The converter circuit comprises: manipulation circuit elements (28, 30 and 32) which define respective propagation paths through the converter circuit (4) for the aforesaid control signals. A logic network (34 to 42) may assume three states, corresponding, respectively, to said first, second and third ratios between the frequencies of said clock signals (clock_1, clock_2), interposing selectively said manipulation elements (28, 30, 32) in the aforesaid propagation paths.

    6.
    发明专利
    未知

    公开(公告)号：DE60217286T2

    公开(公告)日：2007-10-25

    申请号：DE60217286

    申请日：2002-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： URZI IGNAZIO ,  FIENI MASSIMILIANO ,  PISASALE SALVATORE

    IPC: G06F1/12 ,  G06F5/06

    Abstract: A converter circuit for performing transfer of control logic signals between one first device (2) and one second device (3) coming under an interconnection bus, the first device (2) operating the frequency of a first clock signal (clock_1) and the second device (3) operating at the frequency of a second clock signal (clock_2). The clock frequencies in question may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The control signals comprise: an access-request signal (req_1, req_2) to be transferred from the first device (2) to the second device (3) ; a grant signal (gnt_1, gnt_2) to be transferred from the second device (3) to the first device (2); and a response-to-request signal (r_req_1, r_req_2) to be transferred from the second device (3) to the first device (2). The converter circuit comprises: manipulation circuit elements (28, 30 and 32) which define respective propagation paths through the converter circuit (4) for the aforesaid control signals. A logic network (34 to 42) may assume three states, corresponding, respectively, to said first, second and third ratios between the frequencies of said clock signals (clock_1, clock_2), interposing selectively said manipulation elements (28, 30, 32) in the aforesaid propagation paths.

    9.
    发明专利
    未知

    公开(公告)号：DE60026908D1

    公开(公告)日：2006-05-18

    申请号：DE60026908

    申请日：2000-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SCANDURRA ALBERTO ,  PISASALE SALVATORE

    IPC: G06F13/362

    Abstract: An interconnect system includes an arbitration unit (AU) for arbitration among a plurality of sources or initiators requesting (102) access to resources or targets. The arbitration unit (AU) selectively grants (104) the initiators access to the targets as a function of respective priorities. The system includes a programmable control unit (CU) for programmably choosing the priorities in question out of group of at least two different priority schemes including a positional fixed priority, programmed fixed priority, and a variable priority based on a respective threshold latency values associated to the initiators.

Patent Agency Ranking