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    3.
    发明专利
    未知

    公开(公告)号：DE60209465D1

    公开(公告)日：2006-04-27

    申请号：DE60209465

    申请日：2002-09-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOARIN GIANLUIGI ,  ADDUCI FRANCESCO ,  ODDICINI MATTIA ,  CRUDO SALVATORE MATTEO

    IPC: H04B15/02 ,  H03K7/08 ,  H04B1/40

    Abstract: The present invention relates to a high speed interface for radio systems, in particular to a synchronous serial digital interface for car radio. In an its embodiment the synchronous serial digital interface for at least dual radio receiver systems comprises a master device and a slave device; said dual radio receiver systems having an intermediate frequency; said master device and said slave device exchange data in bi-directional way on at least one communication channel; said master device and said slave device have a unique bit clock; said master device supply to said slave device a synchronisation signal; said synchronisation signal have frequency spectrum with an amplitude at said intermediate frequency lower than at the other frequencies.

    4.
    发明专利
    未知

    公开(公告)号：DE69532377D1

    公开(公告)日：2004-02-05

    申请号：DE69532377

    申请日：1995-10-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GAIBOTTI MAURIZIO ,  ADDUCI FRANCESCO

    IPC: H03K3/3562

    Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section (100) and a slave section (200); the master section comprises a master latch structure (5) and the slave section comprises a slave latch structure (6); the master structure (100) and the slave structure (100) are interposed between a power supply line (VDD) and a ground line (7), and each structure is constituted by a first pair of transistors (8, 9; 12, 13) and by a second pair of transistors (10, 11; 14, 15). The particularity of the invention is that in the master latch structure (5) the transistors (8, 9) the source terminals whereof are connected to the power supply line (VDD) and constitute a first one of the two pairs of transistors (8, 9; 10, 11) are P-channel MOS transistors, the source terminals of the second pair of transistors (10, 11) of the master latch structure (5) are connected to the respective drain terminals of an additional pair of transistors (24, 25), the source terminals whereof are connected to the ground line (7); same-phase clock signals (CK) are fed both to the master section (100) and to the slave section (200).

    5.
    发明专利
    未知

    公开(公告)号：DE69426875T2

    公开(公告)日：2001-06-21

    申请号：DE69426875

    申请日：1994-07-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ADDUCI FRANCESCO

    IPC: H03B5/36 ,  H03B1/00

    Abstract: A one-pin integrateable crystal oscillator in a Colpitts configuration employs a differential amplifier as an input gain stage provided with a capacitive-transformer feedback network. An enhanced stability and independence from temperature variation, a high Q figure and a short start-up are achieved without requiring a relatively large area of integration.

    9.
    发明专利
    未知

    公开(公告)号：DE69426875D1

    公开(公告)日：2001-04-19

    申请号：DE69426875

    申请日：1994-07-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ADDUCI FRANCESCO

    IPC: H03B5/36 ,  H03B1/00

    Abstract: A one-pin integrateable crystal oscillator in a Colpitts configuration employs a differential amplifier as an input gain stage provided with a capacitive-transformer feedback network. An enhanced stability and independence from temperature variation, a high Q figure and a short start-up are achieved without requiring a relatively large area of integration.

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