公开(公告)号：JPH0593759A

公开(公告)日：1993-04-16

申请号：JP27379191

申请日：1991-10-22

Applicant: ST MICROELECTRONICS SRL

Inventor： SCARRA FLAVIO ,  GAIBOTTI MAURIZIO

IPC: G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  G06F15/78 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE: To obtain a scanning path type operation analyzer which can separately analyze the different functional blocks of an integrated circuit and has a single scanning clock and a single output phase. CONSTITUTION: An operation analyzer is constituted of a series of first scanning cells 2 positioned to stimulus inputs for the functional blocks of an integrated circuit and a series of second scanning cells 3 positioned to the assessing outputs and each cell 2 and 3 is composed of a master section M, a slave section S, and switching means 8 and 50 which alternately enable the sections M and S under the presence of master and slave clock signals matching the corresponding phases of a scanning clock signal SCK substantially having a square waveform. A clock generating means is interlocked with each pair of scanning cells 2 and 3 so as to locally obtain the master and slave clocks from the scanning clock SCK.

公开(公告)号：DE60102212T2

公开(公告)日：2005-01-27

申请号：DE60102212

申请日：2001-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ZERILLI TOMMASO ,  GAIBOTTI MAURIZIO

IPC: H03K4/00 ,  H03K17/16 ,  H03K4/502

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

公开(公告)号：DE69532377D1

公开(公告)日：2004-02-05

申请号：DE69532377

申请日：1995-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： GAIBOTTI MAURIZIO ,  ADDUCI FRANCESCO

IPC: H03K3/3562

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section (100) and a slave section (200); the master section comprises a master latch structure (5) and the slave section comprises a slave latch structure (6); the master structure (100) and the slave structure (100) are interposed between a power supply line (VDD) and a ground line (7), and each structure is constituted by a first pair of transistors (8, 9; 12, 13) and by a second pair of transistors (10, 11; 14, 15). The particularity of the invention is that in the master latch structure (5) the transistors (8, 9) the source terminals whereof are connected to the power supply line (VDD) and constitute a first one of the two pairs of transistors (8, 9; 10, 11) are P-channel MOS transistors, the source terminals of the second pair of transistors (10, 11) of the master latch structure (5) are connected to the respective drain terminals of an additional pair of transistors (24, 25), the source terminals whereof are connected to the ground line (7); same-phase clock signals (CK) are fed both to the master section (100) and to the slave section (200).

公开(公告)号：ITMI992149D0

公开(公告)日：1999-10-14

申请号：ITMI992149

申请日：1999-10-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO ,  ZERILLI TOSSAMO

IPC: G11C7/06 ,  G11C7/14

Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

公开(公告)号：DE602004004597T2

公开(公告)日：2007-11-15

申请号：DE602004004597

申请日：2004-10-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PISASALE MICHELANGELO ,  GAIBOTTI MAURIZIO ,  LA PLACA MICHELE

IPC: G11C5/14 ,  G11C16/30

Abstract: A voltage-down converter ( 125 ) for providing an output voltage (Vo) lower than a power supply voltage (Vdd) of the converter is proposed. The converter includes voltage regulation means ( 205 ) for obtaining an intermediate voltage (Vr) corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element ( Tr ) with a control signal (Vg) resulting from a comparison between the intermediate voltage (Vr) and a reference voltage (Vbg), and an output stage ( 220,225 1 - 225 N ) for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element ( Tsb,T 1 - T N ) with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set ( MM,ML,MH ) of multiple basic modules ( 225 1 - 225 N ), the converter further including means ( 230,SW 1 - SW N ) for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.

公开(公告)号：DE69129728D1

公开(公告)日：1998-08-13

申请号：DE69129728

申请日：1991-10-15

Applicant: ST MICROELECTRONICS SRL

Inventor： SCARRA FLAVIO ,  GAIBOTTI MAURIZIO

IPC: G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  G06F15/78 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G06F11/26

Abstract: The device comprises a first chain of scanning cells (2) located at the stimulation input of each respective functional block (1) of the integrated circuit and a second chain of scanning cells (3) located at the assessment output of each respective functional block (1) of the integrated circuit. Each cell (2, 3) comprises a master part (M), a slave part (S) and switching means (8, 50) to alternately enable said master (M) and slave parts (S) under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal (SCK) having a substantially square wave. With each pair of chains of scanning cells (2, 3) there are associated clock generation means (25, 26) to locally obtain said master and slave clocks from said scanning clock (SCK).

公开(公告)号：ITVA20020017A1

公开(公告)日：2003-08-21

申请号：ITVA20020017

申请日：2002-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PAPPALARDO DOMENICO ,  GAIBOTTI MAURIZIO

IPC: H02M3/07

Abstract: The charge pump uses PMOS transistors for implementing the first and the second charge transfer switches of the charge pump. Substantially, the closing and opening of the first switch through which the first capacitor is charged, of the second switch for transferring the electric charge from the first capacitor to the load capacitance connected to the output node of the circuit and of the third switch for discharging to ground the load capacitance, are driven by a logic NOR gate. A first input of the NOR gate is connected to a common control node of the PMOS transistor forming the second switch and of a NMOS transistor forming the third switch, a second inverting input is connected to the output node, and the output is connected to the first capacitor.

公开(公告)号：DE602004004597D1

公开(公告)日：2007-03-22

申请号：DE602004004597

申请日：2004-10-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PISASALE MICHELANGELO ,  GAIBOTTI MAURIZIO ,  LA PLACA MICHELE

IPC: G11C5/14 ,  G11C16/30

Abstract: A voltage-down converter ( 125 ) for providing an output voltage (Vo) lower than a power supply voltage (Vdd) of the converter is proposed. The converter includes voltage regulation means ( 205 ) for obtaining an intermediate voltage (Vr) corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element ( Tr ) with a control signal (Vg) resulting from a comparison between the intermediate voltage (Vr) and a reference voltage (Vbg), and an output stage ( 220,225 1 - 225 N ) for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element ( Tsb,T 1 - T N ) with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set ( MM,ML,MH ) of multiple basic modules ( 225 1 - 225 N ), the converter further including means ( 230,SW 1 - SW N ) for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.

公开(公告)号：DE69827109D1

公开(公告)日：2004-11-25

申请号：DE69827109

申请日：1998-02-13

Applicant: ST MICROELECTRONICS SRL

Inventor： GAIBOTTI MAURIZIO ,  DEMANGE NICOLAS

IPC: G11C7/06 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C16/06

Abstract: Sense amplifier circuit for non-volatile memories, of the type apt to draw a reference current from a reference bitline and a cell current from a cell array bitline, and compare them by means of current-voltage converting means and an amplifying stage, said current-voltage converting means comprising also fixing means of a determined voltage on the reference bitline and on the cell array bitline, load circuit means for the reference bitline and the cell array bitline, current mirror circuits for mirroring the reference current into a input node of the amplifying stage and the cell current into a further input of said amplifying stage. According to the invention the load circuit means of the reference bitline (BLREF) and the mirroring means (MR) of the reference current are different circuits and the reference bitline load circuit means are represented by a transistor (P3) which mirrors a predetermined current (IP), generated outside of the sense amplifier circuit (3), in order to have a lower voltage drop on said load circuit means (P3).

公开(公告)号：DE60102212D1

公开(公告)日：2004-04-08

申请号：DE60102212

申请日：2001-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ZERILLI TOMMASO ,  GAIBOTTI MAURIZIO

IPC: H03K4/00 ,  H03K17/16 ,  H03K4/502

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.