公开(公告)号：DE60140757D1

公开(公告)日：2010-01-21

申请号：DE60140757

申请日：2001-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： ZAMBRANO RAFFAELE ,  ARTONI CESARE

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/51

Abstract: A memory cell (30) of a stacked type is formed by a MOS transistor (32) and a ferroelectric capacitor (33). The MOS transistor (32) is formed in an active region (40) of a substrate (30) of semiconductor material and comprises a conductive region (34a). The ferroelectric capacitor (33) is formed on top of the active region and comprises a first and a second electrodes (45, 47) separated by a ferroelectric region (46). A contact region (44a) connects the conductive region (34a) of the MOS transistor to the first electrode (45) of the ferroelectric capacitor (33). The ferroelectric capacitor (33) has a non-planar structure, formed by a horizontal portion (45) and two side portions (48) extending transversely to, and in direct electrical contact with, the horizontal portion.