公开(公告)号：DE60325576D1

公开(公告)日：2009-02-12

申请号：DE60325576

申请日：2003-07-16

Applicant: ST MICROELECTRONICS SRL

Inventor： MARTINELLI ANDREA ,  BALLUCHI DANIELE ,  VILLA CORRADO

IPC: G11C29/00 ,  G11C7/00

Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors (S1-Sn) and, associated with each memory sector, a respective memory location selector (1031-103n) for selecting memory locations within the memory sector according to an address (ADD). The redundancy scheme comprises at least one redundant memory sector (RS1-RSm) adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry (111) for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means (1131-113n) are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line (VXR). A memory sector unusable status indicator element (211) is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.

公开(公告)号：ITMI20070787A1

公开(公告)日：2008-10-18

申请号：ITMI20070787

申请日：2007-04-17

Applicant: ST MICROELECTRONICS SRL

Inventor： BALLUCHI DANIELE ,  MIRICHIGNI GRAZIANO

公开(公告)号：DE60017704D1

公开(公告)日：2005-03-03

申请号：DE60017704

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： BALLUCHI DANIELE

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/00

Abstract: A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage (21), a second level decoder stage (22), and a plurality of bit selection stages (24), each comprising a plurality of selection branches (32a, 32b, 32c, 32d); wherein each selection branch is connected to a respective input of a multiplexer (33) and has a plurality of first level selector stages (35) and a second level selector stage (36, 48). Each second level selector stage (36, 48) comprises a first addressing selector (41) for addressing a first group of bit lines (30). Each bit selection stage (24) further comprises a second addressing selector (42) for addressing a second group of bit lines (30), current and next page selectors (45, 46) for selecting one of the first and second groups of bit lines (30).