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    3.
    发明专利
    未知

    公开(公告)号：DE602004009078T2

    公开(公告)日：2008-06-19

    申请号：DE602004009078

    申请日：2004-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MIRICHIGNI GRAZIANO ,  MARTINELLI ANDREA

    IPC: G11C16/24

    Abstract: A semiconductor memory device (100) is disclosed. The semiconductor memory device includes a plurality of memory cells (110), arranged according to a plurality of rows and a plurality of column. The memory devices further includes a plurality of bit lines (BL1), each bit line being associated with a respective column of said plurality, and a selecting structure (130b) of the bit lines, to select at least one among said bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit (210, CL1, CL0, C 1 , C 2 ), adapted to causing the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

    5.
    发明专利
    未知

    公开(公告)号：DE602006013935D1

    公开(公告)日：2010-06-10

    申请号：DE602006013935

    申请日：2006-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINELLI ANDREA ,  SCHIPPERS STEFAN ,  ONORATO MARCO

    IPC: G11C11/56

    Abstract: Method for programming a memory device (30) of the type comprising a matrix of memory cells (35) divided in buffers of cells (35) capacitively uncoupled from each other, the method comprising the steps of: - first programming of said cells (35) belonging to a buffer (B); - second programming of said cells (35) belonging to said buffer (B); said step of first programming occurs with a ramp gate voltage having first pitch (p1) and programs said cells of said buffer (B) with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch (p2) lower than the pitch (p1). The invention also relates to a memory device suitable for implementing the method proposed.

    6.
    发明专利
    未知

    公开(公告)号：DE60325576D1

    公开(公告)日：2009-02-12

    申请号：DE60325576

    申请日：2003-07-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINELLI ANDREA ,  BALLUCHI DANIELE ,  VILLA CORRADO

    IPC: G11C29/00 ,  G11C7/00

    Abstract: A redundancy scheme for a memory integrated circuit having at least two memory sectors (S1-Sn) and, associated with each memory sector, a respective memory location selector (1031-103n) for selecting memory locations within the memory sector according to an address (ADD). The redundancy scheme comprises at least one redundant memory sector (RS1-RSm) adapted to functionally replace one of the at least two memory sectors, and a redundancy control circuitry (111) for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector; the redundancy control circuitry detects an access request to a memory location within the unusable memory sector and diverts the access request to a corresponding redundant memory location in the redundant memory sector. Associated with each memory location selector, respective power supply control means (1131-113n) are provided adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line (VXR). A memory sector unusable status indicator element (211) is associated with each memory sector, for controlling the respective power supply control means so as to cause, when set, the selective disconnection of the respective memory location selector from the power supply distribution line.

    7.
    发明专利
    未知

    公开(公告)号：DE602004009078D1

    公开(公告)日：2007-10-31

    申请号：DE602004009078

    申请日：2004-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MIRICHIGNI GRAZIANO ,  MARTINELLI ANDREA

    IPC: G11C16/24

    Abstract: A semiconductor memory device (100) is disclosed. The semiconductor memory device includes a plurality of memory cells (110), arranged according to a plurality of rows and a plurality of column. The memory devices further includes a plurality of bit lines (BL1), each bit line being associated with a respective column of said plurality, and a selecting structure (130b) of the bit lines, to select at least one among said bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit (210, CL1, CL0, C 1 , C 2 ), adapted to causing the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

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