公开(公告)号：WO2007096919A8

公开(公告)日：2007-12-13

申请号：PCT/IT2006000114

申请日：2006-02-27

Applicant: ST MICROELECTRONICS SRL ,  BOLLATI GIACOMINO ,  BOSI ALESSANDRO ,  CESURA GIOVANNI ANTONIO

Inventor： BOLLATI GIACOMINO ,  BOSI ALESSANDRO ,  CESURA GIOVANNI ANTONIO

IPC: G11B9/02

CPC classification number: B82Y10/00 ,  G11B5/86 ,  G11B9/02 ,  G11B9/1418 ,  G11B11/002

Abstract: A transducer (3) for a storage medium (5) is provided with a supporting element (9) positione

Abstract translation: 用于存储介质（5）的传感器（3）设置有支撑元件（9）

公开(公告)号：DE60310026D1

公开(公告)日：2007-01-11

申请号：DE60310026

申请日：2003-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CESURA GIOVANNI ,  PANIGADA ANDREA ,  BOSI ALESSANDRO

IPC: H03M1/06 ,  H03M1/16

Abstract: An analog-to-digital converter (200) with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution is proposed. The converter includes a plurality of stages (1053-1050) each one having means (110,115) for converting an analog local signal into a digital local signal with a local resolution lower than said resolution, means (120,125) for determining an analog residue indicative of a quantization error of the means for converting, and means (130) for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and further includes means (204) for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain. In the converter of the invention, the means for combining includes, for at least one of the stages (1053), means (205-240) for dynamically estimating a digital correction signal indicative of an analog error of the corresponding inter-stage gain, and means (230) for controlling the digital weight according to the digital correction signal.