公开(公告)号：JP2000332121A

公开(公告)日：2000-11-30

申请号：JP37172499

申请日：1999-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： GUARDIANI CARLO ,  BURGER ROBERTA ,  ZAFALON ROBERTO ,  VEGGETTI ANDREA ,  DRAGONE NICOLA

IPC: H01L21/82 ,  G06F17/50

Abstract: PROBLEM TO BE SOLVED: To obtain a process for electric circuit design which temporarily analyzes an electric circuit and supplies multiple supply voltages to multiple circuit blocks of the electric circuit according to the temporary analysis. SOLUTION: This method reduces the power consumption of the electric circuit 10 which has a primary supply voltage Vdd, and 1st circuit blocks 16 and 18 and a 2nd circuit block 12. This method includes a stage for determining the operation time of the 1st critical path of the 1st circuit blocks and a stage for determining the operation time of the 2nd critical path of the 2nd circuit block. It is determined from those operation times that the operation time of the 1st critical path is shorter than the operation time of the 2nd critical path. Then a 1st supply voltage lower than the primary supply voltage is generated as to the 1st circuit blocks in response to the decision that the operation time of the 1st critical path is shorter than the operation time of the 2nd critical path.

公开(公告)号：IT1304060B1

公开(公告)日：2001-03-07

申请号：ITMI982844

申请日：1998-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： BURGER ROBERTA

IPC: H03K3/356 ,  H03K17/10

Abstract: A voltage level shifter and an associated level shifting method for shifting from a low voltage input signal to a high voltage output signal are discussed. The level shifter includes a voltage shifting stage having first and second control input nodes and an output node at which the output signal is produced based on control signals received at the control input nodes. The level shifter also includes first and second input inverters coupled in series between the input node and the first control input node; and a third input inverter coupled between the input node and the second control input node. The second inverter can include complementary first and second transistors each with control terminals coupled to an output of the first inverter. The first transistor has a first terminal coupled to the input node and is structured to pass the input signal to the first control input node based on a logic value of a signal output by the first inverter. The third inverter can include complementary third and fourth transistors each with control terminals coupled to the input node. The third transistor has a first-t terminal coupled to the output of the first inverter-and is structured to pass the signal output by the first inverter to the second control input node based on a logic value of the input signal.

公开(公告)号：ITMI982844A1

公开(公告)日：2000-06-29

申请号：ITMI982844

申请日：1998-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： BURGER ROBERTA

IPC: H03K3/356 ,  H03K17/10

Abstract: A voltage level shifter and an associated level shifting method for shifting from a low voltage input signal to a high voltage output signal are discussed. The level shifter includes a voltage shifting stage having first and second control input nodes and an output node at which the output signal is produced based on control signals received at the control input nodes. The level shifter also includes first and second input inverters coupled in series between the input node and the first control input node; and a third input inverter coupled between the input node and the second control input node. The second inverter can include complementary first and second transistors each with control terminals coupled to an output of the first inverter. The first transistor has a first terminal coupled to the input node and is structured to pass the input signal to the first control input node based on a logic value of a signal output by the first inverter. The third inverter can include complementary third and fourth transistors each with control terminals coupled to the input node. The third transistor has a first-t terminal coupled to the output of the first inverter-and is structured to pass the signal output by the first inverter to the second control input node based on a logic value of the input signal.