公开(公告)号：JP2000332121A

公开(公告)日：2000-11-30

申请号：JP37172499

申请日：1999-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： GUARDIANI CARLO ,  BURGER ROBERTA ,  ZAFALON ROBERTO ,  VEGGETTI ANDREA ,  DRAGONE NICOLA

IPC: H01L21/82 ,  G06F17/50

Abstract: PROBLEM TO BE SOLVED: To obtain a process for electric circuit design which temporarily analyzes an electric circuit and supplies multiple supply voltages to multiple circuit blocks of the electric circuit according to the temporary analysis. SOLUTION: This method reduces the power consumption of the electric circuit 10 which has a primary supply voltage Vdd, and 1st circuit blocks 16 and 18 and a 2nd circuit block 12. This method includes a stage for determining the operation time of the 1st critical path of the 1st circuit blocks and a stage for determining the operation time of the 2nd critical path of the 2nd circuit block. It is determined from those operation times that the operation time of the 1st critical path is shorter than the operation time of the 2nd critical path. Then a 1st supply voltage lower than the primary supply voltage is generated as to the 1st circuit blocks in response to the decision that the operation time of the 1st critical path is shorter than the operation time of the 2nd critical path.

公开(公告)号：DE69734099D1

公开(公告)日：2005-10-06

申请号：DE69734099

申请日：1997-06-27

Applicant: ST MICROELECTRONICS SRL

Inventor： DELL ORO ANNALISA ,  VEGGETTI ANDREA

IPC: H04J3/00 ,  H04J3/16 ,  H04Q11/04

Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard, being of a type which comprises an input portion (3) and an output portion (4). It is characterized by being constructed of at least one modular component (2) adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.