公开(公告)号：DE60011035T2

公开(公告)日：2004-09-16

申请号：DE60011035

申请日：2000-03-02

Applicant: ST MICROELECTRONICS SRL

Inventor： DE AMBROGGI LUCA GIUSEPPE ,  CAMPANELE FABRIZIO ,  KUMAR PROMOD ,  NICOSIA SALVATORE ,  TOMAIUOLO FRANCESCO

IPC: G11C29/00 ,  G06F11/20

Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).

公开(公告)号：DE60011035D1

公开(公告)日：2004-07-01

申请号：DE60011035

申请日：2000-03-02

Applicant: ST MICROELECTRONICS SRL

Inventor： DE AMBROGGI LUCA GIUSEPPE ,  CAMPANELE FABRIZIO ,  KUMAR PROMOD ,  NICOSIA SALVATORE ,  TOMAIUOLO FRANCESCO

IPC: G11C29/00 ,  G06F11/20

Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).