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公开(公告)号：JP2001243778A
公开(公告)日：2001-09-07
申请号：JP2001022134
申请日：2001-01-30
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPANALE FABRIZIO , TOMAIUOLO FRANCESCO , NICOSIA SALVATORE , DE AMBROGGI LUCA GIUSEPPE , KUMAR PROMOD , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To provide a multi-purpose memory device suitable for an application example of a wider range independently of whether reading of data is required or not in the asynchronous mode (as in standard memory) in random access or in a synchronous progressive mode in burst type access. SOLUTION: A memory device recognizes modes of access and reading required by a microprocessor, also enables performing self-conditioning of its internal circuit based on such a recognition to perform reading data in a required mode. At the time, an additional external control signal is not required, and sacrifice is not forced in an access time and a reading time as compared with obtained one in the case of a memory device constituted specifically for any one of operation modes for constitution of the same manufacturing technology and conventional technology.
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公开(公告)号：DE60306488D1
公开(公告)日：2006-08-10
申请号：DE60306488
申请日：2003-02-27
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：DE60011035T2
公开(公告)日：2004-09-16
申请号：DE60011035
申请日：2000-03-02
Applicant: ST MICROELECTRONICS SRL
Inventor： DE AMBROGGI LUCA GIUSEPPE , CAMPANELE FABRIZIO , KUMAR PROMOD , NICOSIA SALVATORE , TOMAIUOLO FRANCESCO
Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).
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公开(公告)号：DE60011035D1
公开(公告)日：2004-07-01
申请号：DE60011035
申请日：2000-03-02
Applicant: ST MICROELECTRONICS SRL
Inventor： DE AMBROGGI LUCA GIUSEPPE , CAMPANELE FABRIZIO , KUMAR PROMOD , NICOSIA SALVATORE , TOMAIUOLO FRANCESCO
Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).
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公开(公告)号：ITVA20000015A1
公开(公告)日：2001-11-30
申请号：ITVA20000015
申请日：2000-05-30
Applicant: ST MICROELECTRONICS SRL
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Patent Agency Ranking
公开(公告)号：DE60044895D1
公开(公告)日：2010-10-14
申请号：DE60044895
申请日：2000-04-17
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：DE60043212D1
公开(公告)日：2009-12-10
申请号：DE60043212
申请日：2000-04-27
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：DE60019081D1
公开(公告)日：2005-05-04
申请号：DE60019081
申请日：2000-01-31
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：ITVA20000011A1
公开(公告)日：2001-11-19
申请号：ITVA20000011
申请日：2000-05-17
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：ITVA20000015D0
公开(公告)日：2000-05-30
申请号：ITVA20000015
申请日：2000-05-30
Applicant: ST MICROELECTRONICS SRL
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