公开(公告)号：DE69229118T2

公开(公告)日：1999-08-26

申请号：DE69229118

申请日：1992-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： VARAMBALLY RAJAMOHAN ,  BARONI ANDREA ,  CARRO LUIGI ,  MASTRODOMENICO GIOVANNI MASTRO ,  TAGLIERCIO MICHELE C O SGS-THO ,  CAPOCELLI PIERO C O SGS-THOMSO

IPC: G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

Abstract: A single-port RAM generator architecture, intended to generate different RAMs structures in a CAD enviroment, and being of the type comprising a Static RAM (2) matrix and a self timed architecture (3), comprises also a control logic (10), a dummy row (7) and a dummy column (9) having respectively equivalent load of a word line and of bit column of said matrix (2). The dummy column (9) is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer choise gives different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

公开(公告)号：DE69229118D1

公开(公告)日：1999-06-10

申请号：DE69229118

申请日：1992-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： VARAMBALLY RAJAMOHAN ,  BARONI ANDREA ,  CARRO LUIGI ,  MASTRODOMENICO GIOVANNI MASTRO ,  TAGLIERCIO MICHELE C O SGS-THO ,  CAPOCELLI PIERO C O SGS-THOMSO

IPC: G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

Abstract: A single-port RAM generator architecture, intended to generate different RAMs structures in a CAD enviroment, and being of the type comprising a Static RAM (2) matrix and a self timed architecture (3), comprises also a control logic (10), a dummy row (7) and a dummy column (9) having respectively equivalent load of a word line and of bit column of said matrix (2). The dummy column (9) is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer choise gives different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.