公开(公告)号：JPH10302479A

公开(公告)日：1998-11-13

申请号：JP8093998

申请日：1998-03-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BARONI ANDREA ,  RIMONDI DANILO ,  TALIERCIO MICHELE ,  TORELLI COSIMO

IPC: G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To reduce current consumption in the write mode by installing a dummy memory train roughly the same as the memory cell to monitor the switching time of the dummy memory and selecting the short time alone strictly required for the operation that the desired line to be programmed switches the memory cell to the desired state. SOLUTION: The device is provided with a memory cell 2, a dummy memory train DC(DMCD0-DMCn) roughly the same as the memory cell and plural gates RD1-RDn which transfer the selected output of the line decoder 3 to the lines. The pre-charge control means 4' pre-charges the dummy train DC to the first logic state when the line is not selected. The detecting means DET1 detects the state where the dummy train DC is discharged from the pre-charge potential to the programming potential by the programming means which makes the dummy train DC correspond to the second logic state contrary to the first one to enable plural gates RD1-RDn and disable them after transferring to the second logic state.

公开(公告)号：JPH076182A

公开(公告)日：1995-01-10

申请号：JP29335193

申请日：1993-11-24

Applicant: ST MICROELECTRONICS SRL

Inventor： VERAMBALLY RAJAMOHAN ,  BARONI ANDREA ,  CARRO LUIGI ,  MASTRODOMENICO GIOVANNI ,  TALIERCIO MICHELE ,  CAPOCELLI PIERO

IPC: G06F17/50 ,  G11C7/14 ,  G11C7/22

Abstract: PURPOSE: To provide a single-port RAM generator having such structural and functional features that give a change to a parameter introduced by a user. CONSTITUTION: A single-port RAM generator 1 includes an SRAM matrix 2 and a self-timer 3 and the timer 3 has dummy rows 7 and dummy columns 9. The rows 7 and columns 9 of the timer 3 respectively have loads equivalent to those of one word line and one bit column and the dummy columns are discharged at speeds faster than those of the dummy columns.

公开(公告)号：DE69229118T2

公开(公告)日：1999-08-26

申请号：DE69229118

申请日：1992-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： VARAMBALLY RAJAMOHAN ,  BARONI ANDREA ,  CARRO LUIGI ,  MASTRODOMENICO GIOVANNI MASTRO ,  TAGLIERCIO MICHELE C O SGS-THO ,  CAPOCELLI PIERO C O SGS-THOMSO

IPC: G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

Abstract: A single-port RAM generator architecture, intended to generate different RAMs structures in a CAD enviroment, and being of the type comprising a Static RAM (2) matrix and a self timed architecture (3), comprises also a control logic (10), a dummy row (7) and a dummy column (9) having respectively equivalent load of a word line and of bit column of said matrix (2). The dummy column (9) is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer choise gives different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

公开(公告)号：DE69229118D1

公开(公告)日：1999-06-10

申请号：DE69229118

申请日：1992-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： VARAMBALLY RAJAMOHAN ,  BARONI ANDREA ,  CARRO LUIGI ,  MASTRODOMENICO GIOVANNI MASTRO ,  TAGLIERCIO MICHELE C O SGS-THO ,  CAPOCELLI PIERO C O SGS-THOMSO

IPC: G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

Abstract: A single-port RAM generator architecture, intended to generate different RAMs structures in a CAD enviroment, and being of the type comprising a Static RAM (2) matrix and a self timed architecture (3), comprises also a control logic (10), a dummy row (7) and a dummy column (9) having respectively equivalent load of a word line and of bit column of said matrix (2). The dummy column (9) is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer choise gives different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

公开(公告)号：DE69727059D1

公开(公告)日：2004-02-05

申请号：DE69727059

申请日：1997-10-20

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPOCELLI PIERO ,  TALIERCIO MICHELE ,  VARAMBALLY RAJAMOHAN ,  BARONI ANDREA

IPC: G11C29/00 ,  G06F17/50

公开(公告)号：DE69723226D1

公开(公告)日：2003-08-07

申请号：DE69723226

申请日：1997-04-03

Applicant: ST MICROELECTRONICS SRL

Inventor： BARONI ANDREA ,  RIMONDI DANILO ,  TALIERCIO MICHELE ,  TORELLI COSIMO

IPC: G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00 ,  G11C11/409

Abstract: A memory device comprises an array (1) of memory cells (2,DMC0-DMCn) arranged in rows (R1-Rn) and columns (C1-Cm,DC), a plurality of gates (RD1-RDn) for transmitting respective selection outputs (RS1-RSn) of a row decoder (3) to respective rows (RS), a dummy column (DC) of dummy memory cells (DMC0-DMCn) substantially indentical to the memory cells, precharge means (P4,P5,P6,P7) for precharging the columns and the dummy column at a precharge potential (VDD) when no row is selected, and programming means (N7,N8,7) for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means (P3) for presetting the dummy memory cells in a first logic state when no row is selected; dummy column programming means (N9,N10) for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state; first detector means (DET1) for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of said gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from said first logic state to said second logic state.