公开(公告)号：JPH0276255A

公开(公告)日：1990-03-15

申请号：JP19648289

申请日：1989-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： BERGONZONI CARLO ,  CAVIONI TIZIANA ,  CRISENZA GIUSEPPE PAOLO

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/105

Abstract: PURPOSE: To attain a desired threshold voltage value without using an additional mask by a method wherein, after a deep well diffusion part is formed, ion implantation with unmasked dopants of first polarity is made on the entire surface of a silicon substrate. CONSTITUTION: An n-well CMOS device having a gate for a device of a 'low' supply voltage and a gate for a device of a 'high' supply voltage is manufactured. After a deep n-well diffusion part is formed, boron is implanted on the entire substrate by using dose, whereby a series of devices are manufactured. The other series of devices are manufactured by forming p-channel transistors of a buried channel. Thereby, a desired threshold voltage can be obtained.

公开(公告)号：JP2744592B2

公开(公告)日：1998-04-28

申请号：JP31187094

申请日：1994-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  MANZINI STEFANO ,  CAVIONI TIZIANA

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH07254687A

公开(公告)日：1995-10-03

申请号：JP31187094

申请日：1994-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  MANZINI STEFANO ,  CAVIONI TIZIANA

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide an integrated circuit structure, capable of forming a hybrid type integrated circuit having at least one EPROM without adding a special working step for the hybrid type integrated circuit regarding the integrated circuit. CONSTITUTION: An EPROM cell has an active region 18, and the region is formed by the same operation as the formation of a P-type region 17, in which an N -channel MOS transistor is housed. Likewise, each region of sources and drains is formed by the same operation as the formation of the source regions and drain regions 31 of the transistors, control electrodes 15 consisting of N - type regions are shaped by the same operation as the formation of deep regions 14 communicating each N -type embedded region, and floating gate electrodes 24 formed of one conductive material layer are formed by the same operation as the formation of the gate electrodes 23 of the transistors in an integrated circuit.

公开(公告)号：DE69330564T2

公开(公告)日：2002-06-27

申请号：DE69330564

申请日：1993-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  MANZINI STEFANO ,  CAVIONI TIZIANA

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/088

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area (18) formed by the same operations as are necessary to form a P region (17) intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are necessary to form the source and drain regions (31) of said transistor, a control electrode (15) consisting of an N+ region formed by the same operations as are carried out to form deep regions (14) intended to contact buried N+ regions, and a floating gate electrode (24) consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes (23) of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

公开(公告)号：DE69330564D1

公开(公告)日：2001-09-13

申请号：DE69330564

申请日：1993-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  MANZINI STEFANO ,  CAVIONI TIZIANA

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/088

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area (18) formed by the same operations as are necessary to form a P region (17) intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are necessary to form the source and drain regions (31) of said transistor, a control electrode (15) consisting of an N+ region formed by the same operations as are carried out to form deep regions (14) intended to contact buried N+ regions, and a floating gate electrode (24) consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes (23) of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.