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公开(公告)号：JP2648126B2
公开(公告)日：1997-08-27
申请号：JP8842795
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
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公开(公告)号：JPH11355060A
公开(公告)日：1999-12-24
申请号：JP12891199
申请日：1999-05-10
Applicant: ST MICROELECTRONICS SRL
Inventor： CHIOZZI GIORGIO , MARCONE BRUNO
Abstract: PROBLEM TO BE SOLVED: To provide a short-circuit protection circuit especially for a power transistor. SOLUTION: A short circuit protection circuit 10 for a power transistor 12 contains a first circuit which is connected to the power transistor in parallel and which is for mirroring the output current of the power transistor and second mirror circuits 13 and 14 which are connected to the fist mirror means 11 in series. The second mirror circuits output current correlated to current mirrored by the first mirror circuit for comparing it with the reference current Iref. The result of comparison decides whether it is necessary to operate the transistor or not. A circuit which is connected in parallel to the power transistor and the first mirror circuit for adjusting the minimum value and the maximum value of the output current of the power transistor as the function of voltage in the transistor, and which detects the drop of voltage on the power transistor can be contained.
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公开(公告)号：JPH0846462A
公开(公告)日：1996-02-16
申请号：JP8842795
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
Abstract: PURPOSE: To provide a low-frequency amplifier for eliminating negative peak in an output voltage that is easily and widely adaptable. CONSTITUTION: In the low-frequency amplifier 30 which is equipped serially with an input step 2, a voltage amplifier step 3 and an output step 4, other input step 31 is provided to be turned on during a transient term only for preventing a negative voltage peak from being generated by an output terminal 19 during a transient term from the disabled operation condition to the operation condition and thereby a capacitor 18 in the voltage amplifier is charged up to the specified electric charge value.
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公开(公告)号：JPH08130444A
公开(公告)日：1996-05-21
申请号：JP9797695
申请日：1995-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
IPC: H01L27/06 , H01L21/8222 , H03H11/40 , H03K4/06 , H03K4/50
Abstract: PURPOSE: To provide the ramp generator of a small integrated area by arranging N-pieces of transistors of Darlington configuration, which are cascade-connected and H+k-pieces of diodes which are connected in series and which are directly biased. CONSTITUTION: Bipolar PNP transistors TrQ1-Q3 of Darlington configuration, which are cascade-connected, are used. The four diodes D1-D4 of PN junction are directly biased and they are connected in series between a reference current oscillator Ir and an integrated capacitance C. All used TrQ1-Tr3 and four TrD1-D4 in diode forms have the same minimum dimensions to which the manufacture process of an integrated circuit is permitted. Voltage drop V1-V2 passing through the directly biased PN junction of TrQ1-TrQ3 decides the biasing of the four diodes D1-D4 of PN junction, controls current I2 passing through diode chains D1-D4 and charges the capacitance C.
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公开(公告)号：JPH07321568A
公开(公告)日：1995-12-08
申请号：JP12400995
申请日：1995-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
Abstract: PURPOSE: To realize high linearity, small switching distortion, large rate between the maximum output currents and non-operation currents, non-operation currents unrelated with temperature and fluctuation at the time of manufacture, and the simplicity of a circuit in an amplifier equipped with two complementary MOSFET final stage transistors connected in a push-pull type between two power sources. CONSTITUTION: A circuit part for deciding non-operation currents and a circuit part for supplying currents to a load are made independent, and two mutual conductance amplifier circuits Tp, and Tn for controlling two complementary MOSFET final stage transistors Qpf, and Qnf are designed so that a zero output can be provided when they are not in operation, and two voltage generating circuits and two resistance Rp and Rn for deciding the non-operation currents are connected between the gate electrode of the complementary MOSFET final transistors Qpf and Qnf and power sources +VCC and the inverse of VCC.
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Patent Agency Ranking
公开(公告)号：JPH11274495A
公开(公告)日：1999-10-08
申请号：JP1337099
申请日：1999-01-21
Applicant: St Microelectronics Srl , エスティーマイクロエレクトロニクスエス.アール.エル.
Inventor： CHIOZZI GIORGIO , ANDREINI ANTONIO
CPC classification number: H01L27/0251 , H01L29/0619 , H01L29/7809 , H01L29/7811
Abstract: PROBLEM TO BE SOLVED: To avoide an overvoltage between a source and a gate in which a gate dielectric of VDMOS(vertical double diffusion MOS) transistors formed in an active region of an integrated circuit which is junctioned and isolated may be damaged or broken.
SOLUTION: MOS transistors are formed in an active region 13, and the gate electrode is connected to a gate electrode 17 of VDMOS transistors and a source region of the MOS transistors is made common to a source region 9 of the VDMOS trasistors, and drain regions 30, 31 of the MOS transistors are coupled to a junction and isolation region 14. A threshold voltage of the MOS transistors is lower than a breakdown voltage of a gate dielectric of the VDMOS transistors, and the MOS transistors act as a voltage limitter.
COPYRIGHT: (C)1999,JPOAbstract translation: 要解决的问题：为了避免源极和栅极之间的过电压，其中形成在结合和隔离的集成电路的有源区中的VDMOS（垂直双重扩散MOS）晶体管的栅极电介质可能被损坏或破坏。 解决方案：MOS晶体管形成在有源区13中，栅电极连接到VDMOS晶体管的栅电极17，并且MOS晶体管的源极区域与VDMOS晶体管的源极区9相同，漏区 30,31的MOS晶体管耦合到结和隔离区14.MOS晶体管的阈值电压低于VDMOS晶体管的栅极电介质的击穿电压，并且MOS晶体管用作电压限制器。
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公开(公告)号：JP2688477B2
公开(公告)日：1997-12-10
申请号：JP12400995
申请日：1995-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
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公开(公告)号：DE69522454D1
公开(公告)日：2001-10-04
申请号：DE69522454
申请日：1995-10-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CHIOZZI GIORGIO
Abstract: A sensor of instantaneous power dissipable through a power transistor (Pwr) of the MOS type connected between the output terminal (OUT) of a power stage and ground (GND). It comprises a MOS transistor (Q5) having its gate terminal connected to that of the power transistor, source terminal connected to ground, and drain terminal connected to a circuit node (N) which is coupled to the output terminal (OUT) by means of a current mirror circuit (D1,Q2) which includes a resistive element (R) in its input leg. Connected to the circuit node is the base terminal of a bipolar transistor (Q4) which is respectively connected, through a diode (D3) and a constant current generator (Iref) between the output terminal and ground.
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公开(公告)号：DE69421692D1
公开(公告)日：1999-12-23
申请号：DE69421692
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
Abstract: An AB class stage is described which comprises two complementary MOSFET final transistors (Qpf, Qnf) connected in a push-pull manner between two supply terminals (+Vcc, -Vcc). In order to attain high linearity, low switching distortion, a high ratio between the maximum output current and the rest current, independence of the rest current from the temperature and manufacturing variables and a circuit simplicity, the circuits determining the rest current and those which provide current to the load are substantially independent of one another. More particularly, two transconductance amplifiers (Tp, Tn) are provided which control the final transistors (Qpf, Qnf) and are dimensioned so as to have zero output current in rest conditions, two voltage generators (Vref(Qpf), Vref(Qnf)) which determine the rest current and two resistors (Rp, Rn) being connected between the gate electrodes of the final transistors and the supply terminals (+Vcc, -Vcc).
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公开(公告)号：DE69410436T2
公开(公告)日：1998-09-17
申请号：DE69410436
申请日：1994-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
IPC: H01L27/06 , H01L21/8222 , H03H11/40 , H03K4/06 , H03K4/50
Abstract: A circuit for dividing a reference current (Ir) is composed by an n number of transistors (Q1,Q2,Q3) connected in cascade, in a Darlington configuration, between current generator and a fractionary current output node (V2) and by N+k, where k is an integer different from zero, directly biased diodes (D1-D4) in series, connected between the generator and said fractionary current output node. The circuit does not employ current mirrors and conveniently all transistors may have the minimum size of the process, which also minimizes the effects of leakage currents. Additionally, means may be used for compensating the leakage currents from the tubs of the transistors. The circuit is useful as a capacitance multiplier, or as a slow ramp generator in a large number of design situations. Independency from intrinsic parameters of the transistors used and/or from temperature of operation may be provided by employing a specifically designed reference current generating means. Several embodiments are described.
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