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公开(公告)号：JP2648126B2
公开(公告)日：1997-08-27
申请号：JP8842795
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
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公开(公告)号：JP2000244257A
公开(公告)日：2000-09-08
申请号：JP2000034045
申请日：2000-02-10
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , GROSSO ANTONIO
Abstract: PROBLEM TO BE SOLVED: To provide a digital input PWM power amplifier which is operated with high efficiency and by a comparatively low switching frequency. SOLUTION: This digital input PWM power amplifier is provided with an over-sampling noise shaping circuit, a first bus for transmitting the maximum digit bit (most significant bit) of a first number D, the second bus for transmitting the minimum digit bit (least significant bit) of the second number S and first and second PCM/PWM converters for respectively receiving the supply of first and second number bits and outputting PWM signals (MSBdig and LSBdig). The PWM signal(MSBdig) outputted by the first converter is added to the PWMsignal(LSBdig) outputted by the second one on the reverse input node(-) of an output power stage.
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公开(公告)号：JPH0846462A
公开(公告)日：1996-02-16
申请号：JP8842795
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
Abstract: PURPOSE: To provide a low-frequency amplifier for eliminating negative peak in an output voltage that is easily and widely adaptable. CONSTITUTION: In the low-frequency amplifier 30 which is equipped serially with an input step 2, a voltage amplifier step 3 and an output step 4, other input step 31 is provided to be turned on during a transient term only for preventing a negative voltage peak from being generated by an output terminal 19 during a transient term from the disabled operation condition to the operation condition and thereby a capacitor 18 in the voltage amplifier is charged up to the specified electric charge value.
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公开(公告)号：JP2001169383A
公开(公告)日：2001-06-22
申请号：JP2000314791
申请日：2000-10-16
Applicant: ST MICROELECTRONICS SRL
Inventor： RANIERI DANILO , BRAMBILLA DAVIDE , BOTTI EDOARDO , CELANT LUCA
IPC: G01R31/316 , G01R19/165 , G01R31/28 , H03F1/52 , H04R3/00
Abstract: PROBLEM TO BE SOLVED: To provide an audio amplifier where occurrence of an unrecoverable damage to a speaker can be avoided. SOLUTION: A detection interval or phase is established by applying a timing pulse with a frequency to an input of the detection circuit of this invention. The detection circuit detects a rising edge of the timing pulse to set a bistable circuit. A signal on an output node of an amplifier channel is compared with a window denoting a permissible value. After the initialization set, the bistable circuit is reset on the basis of production of a level of an output signal in the window denoting the permissible value. When the bistable circuit cannot be reset before the end of the detection phase, the detection circuit informs a user about the presence of an excessive offset.
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公开(公告)号：JPH06318830A
公开(公告)日：1994-11-15
申请号：JP5275194
申请日：1994-02-24
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , BRASCA GUIDO
Abstract: PURPOSE: To reduce power consumption due to an amplifier operation by using plural operational power amplifiers capable of being connected by configuration. CONSTITUTION: The amplifier comprises power operational amplifiers of OPA+F, OPA-F, OPA-R, OPA+R. Each amplifier is provided with an intrinsic differential feedback loop and furthermore, includes a window comparator to drive switches SW-F, SW-C, SW-R. The OPA+R is provided with a feedback loop either of which is suitable for forming the amplifier as a buffer is selected and the switch driven by the window comparator is configured by the loop. Consequently, either of the switch or a first differential feedback loop DFN+R of the same amplifier is selected.
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Patent Agency Ranking
公开(公告)号：JP2688477B2
公开(公告)日：1997-12-10
申请号：JP12400995
申请日：1995-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
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公开(公告)号：JPH06303047A
公开(公告)日：1994-10-28
申请号：JP5275094
申请日：1994-02-24
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , FASSINA ANDREA , FERRARI PAOLO
IPC: H03F1/52
Abstract: PURPOSE: To protect a power transistor TR of an output stage functionally connected between an output node and a supply rail by short-circuiting the base-emitter junction of a TR under a reverse bias condition on the occurrence of an SPU condition. CONSTITUTION: This device comprises a TR QS which has the emitter connected to a base B1 of a power TR Q1 and has the collector connected to an output node Out and has the base B2 connected to a supply rail Vcc of an amplification circuit. While the device normally functions, the protection TR QS of the same type as the power TR Q1 to be protected is turned off because the potential on the base (node B2 ) is higher than that existing on emitter and collector nodes E and C. Actually, the base potential is practically equal to the supply voltage Vcc of the amplifier.
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公开(公告)号：JP2000151299A
公开(公告)日：2000-05-30
申请号：JP31906499
申请日：1999-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , GROSSO ANTONIO , MASINI MARCO
IPC: H03F3/217
Abstract: PROBLEM TO BE SOLVED: To provide a class D power amplifier which can process an analog or digital input signal without the need to generate a reference waveform. SOLUTION: The amplifier has two identical amplification modules. Each module has a switching output operational amplifier (O1) equipped with a voltage noninverted input terminal (In+), a current mode inverted input terminal (In-), and a loop filter which outputs a signal composed substantially of a triangular waveform and actualizes a single or plural gradient integrator, a cascade (C1) composed of a logic inverter or plural logic inverters which are coupled with the output terminal of the integrator and output logic PWM signals, an output power stage (P1) which converts the logic PWM signal to a PWM signal and switches between the potentials of two supply rails of the circuit, and a feedback resistance (Rf) which connects the output terminal of a power stage (P1) to the inverted input terminal (In-) of the operational amplifier (O1).
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公开(公告)号：JPH08130444A
公开(公告)日：1996-05-21
申请号：JP9797695
申请日：1995-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
IPC: H01L27/06 , H01L21/8222 , H03H11/40 , H03K4/06 , H03K4/50
Abstract: PURPOSE: To provide the ramp generator of a small integrated area by arranging N-pieces of transistors of Darlington configuration, which are cascade-connected and H+k-pieces of diodes which are connected in series and which are directly biased. CONSTITUTION: Bipolar PNP transistors TrQ1-Q3 of Darlington configuration, which are cascade-connected, are used. The four diodes D1-D4 of PN junction are directly biased and they are connected in series between a reference current oscillator Ir and an integrated capacitance C. All used TrQ1-Tr3 and four TrD1-D4 in diode forms have the same minimum dimensions to which the manufacture process of an integrated circuit is permitted. Voltage drop V1-V2 passing through the directly biased PN junction of TrQ1-TrQ3 decides the biasing of the four diodes D1-D4 of PN junction, controls current I2 passing through diode chains D1-D4 and charges the capacitance C.
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公开(公告)号：JPH07321568A
公开(公告)日：1995-12-08
申请号：JP12400995
申请日：1995-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , CHIOZZI GIORGIO
Abstract: PURPOSE: To realize high linearity, small switching distortion, large rate between the maximum output currents and non-operation currents, non-operation currents unrelated with temperature and fluctuation at the time of manufacture, and the simplicity of a circuit in an amplifier equipped with two complementary MOSFET final stage transistors connected in a push-pull type between two power sources. CONSTITUTION: A circuit part for deciding non-operation currents and a circuit part for supplying currents to a load are made independent, and two mutual conductance amplifier circuits Tp, and Tn for controlling two complementary MOSFET final stage transistors Qpf, and Qnf are designed so that a zero output can be provided when they are not in operation, and two voltage generating circuits and two resistance Rp and Rn for deciding the non-operation currents are connected between the gate electrode of the complementary MOSFET final transistors Qpf and Qnf and power sources +VCC and the inverse of VCC.
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