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公开(公告)号:JPH04274516A
公开(公告)日:1992-09-30
申请号:JP28772891
申请日:1991-11-01
Applicant: ST MICROELECTRONICS SRL
Inventor: DELL ORO ANNALISA , DELGROSSI GIOVANNI
Abstract: PURPOSE: To provide a system constitution that can improve the performance concerning the storage capacity and also can reduce the entire scale of a circuit structure. CONSTITUTION: This system constitution is composed of a prescribed number of RAM 14, 15 and 16 which have the single access gates and the storage capacity equal to each part of total capacity that is needed for the system constitution. A control means 5 is added to the system constitution to control the accesses given to those RAMs and therefore to perform the read/write operations at a time or with time delays.
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公开(公告)号:DE69734099D1
公开(公告)日:2005-10-06
申请号:DE69734099
申请日:1997-06-27
Applicant: ST MICROELECTRONICS SRL
Inventor: DELL ORO ANNALISA , VEGGETTI ANDREA
Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard, being of a type which comprises an input portion (3) and an output portion (4). It is characterized by being constructed of at least one modular component (2) adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.
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公开(公告)号:DE69031948T2
公开(公告)日:1998-04-23
申请号:DE69031948
申请日:1990-11-02
Applicant: ST MICROELECTRONICS SRL
Inventor: DELL ORO ANNALISA , DELGROSSI GIOVANNI
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公开(公告)号:DE69031948D1
公开(公告)日:1998-02-19
申请号:DE69031948
申请日:1990-11-02
Applicant: ST MICROELECTRONICS SRL
Inventor: DELL ORO ANNALISA , DELGROSSI GIOVANNI
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