公开(公告)号：JPH07218578A

公开(公告)日：1995-08-18

申请号：JP2865295

申请日：1995-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PENZA LUIGI ,  FAVALLI MICHELE ,  RICCO BRUNO

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H01L21/66

Abstract: PURPOSE: To evaluate the existence of resistant bridging defect by sensing that voltages existing in one or more signal nodes stay within a predetermined intermediate voltage range. CONSTITUTION: An AUX-LINE is connected to one of two supply lines VDD of a functional CMOS or BiCMOS cell of an integrated circuit, or an earth via a load. Respective inverter stages which are input from the output node of a logic cell to be traced are connected to the AUX-LINE and the other of the two lines VDD, and are made of (n) channel and (r) channel transistors. When the voltage of the output node of the logic cell has middle level within a predetermined intermediate voltage range, the respective inverter stages cause the AUX-LINE and the other line VDD to be conductive mutually so that the voltage of the output node can be traced. By matching the trigger levels of the respective inverter stages with the logic threshold level of the logic cell, the accurate selection test of the logic cell can be executed.