公开(公告)号：DE602005017256D1

公开(公告)日：2009-12-03

申请号：DE602005017256

申请日：2005-06-09

Applicant: ST MICROELECTRONICS SRL

Inventor： PERNICI SERGIO ,  GARIBALDI FEDERICO

IPC: H03M3/04

Abstract: A single-loop differential switched-capacitors Sigma-Delta converter has a three stage double-sampling architecture, a reduced current consumption and is stable even for large input dynamics. The latter characteristic makes it suitable for RF applications. The novel three-stage multi-bit double-sampled architecture of a Sigma-Delta converter has a single-loop architecture, that is all integrators are included in a same feedback loop. This has been made possible by an effective choice of the type of integrators of the converter connected in cascade. Thanks to its innovative architecture, the functioning of the converter is less sensitive to non idealities of the operational amplifiers of the integrators.