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公开(公告)号：JP2001016322A
公开(公告)日：2001-01-19
申请号：JP2000125357
申请日：2000-04-26
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , PERNICI SERGIO
Abstract: PROBLEM TO BE SOLVED: To provide a final-stage amplifier and an electroacoustic, transducer whose one terminal is connected to a ground terminal to a reception section of a telephone set and to eliminate a filtering element without causing disturbances. SOLUTION: This reception section is provided with a final-stage amplifier 12, an electroacoustic transducer 13 with a 1st terminal connected to the ground point of the circuit of the reception section, a switch on/off control unit, a reference voltage power supply 30, a switch 21 that selects a 1st position or a 2nd position and selectively connects the 2nd terminal of the electroacoustic transducer 13 to a reference voltage terminal REF or an output terminal OUT of the final-stage amplifier 12 via a capacitor Cest, and a control means 20 that activates or inactivated the final stage amplifier 12 and the reference voltage source 30, in response to a signal PD of the switch on/off control unit and operates the switch 21 according to a prescribed time program. This reception section operates with immunity to disturbances similar to a completely balanced structure, even when the electroacoustic transducer 13 is not connected between two balanced output terminals.
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公开(公告)号：JP2599575B2
公开(公告)日：1997-04-09
申请号：JP29668694
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO
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公开(公告)号：JP2000357975A
公开(公告)日：2000-12-26
申请号：JP2000138330
申请日：2000-05-11
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , PERNICI SERGIO
Abstract: PROBLEM TO BE SOLVED: To prevent influence of improper audible noises which are generated by an electrical disturbance during transient period by adding a delay means to a controller, to generate the control signals to the 1st and 2nd enable/disable means in accordance with a prescribed control program and also to generate control signal of a switching means. SOLUTION: A processor 11 receives a demodulated digital signal RX-IN at its input side and supplies an analog signal, that is balanced between two outputs. The output of the processor 11 is connected to the input side of a differential amplifier 12 and then connected to one of input sides of the amplifier 12 through the resistances R1A and R1B connected in series to the MOS transistor M1A and M1B. An electroacoustic transducer 13 is connected between the output sides 15 and 16 of the amplifier 12. The processor 11 and the amplifier 12 have a circuit means to enable or disable a power supply in accordance with the signals which are applied to the corresponding enable terminals 17 and 18 respectively.
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公开(公告)号：JP2001068938A
公开(公告)日：2001-03-16
申请号：JP2000221032
申请日：2000-07-21
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO , NICOLLINI GERMANO
Abstract: PROBLEM TO BE SOLVED: To provide a receiver of a telephone set that can suppress noise even when one terminal of an electroacoustic transducer is connected to ground without the need for a filter element. SOLUTION: The receiver part of the telephone set is provided with a signal reception and demodulation device 10, a demodulation signal processing unit 11, an operational amplifier 16, an electroacoustic transducer 13, and a controller 20 of the operational amplifier 16, and also with capacitors C3, C4 connected between a 1st input and an output and between a 2nd input and the output of the operational amplifier 16, a capacitor C13 that is switchingly connected between reference voltage terminal pairs or between the 1st input and the output of the operational amplifier 16 with switches S1, S2 and a capacitor C2S that is switchingly connected between other reference voltage terminal pairs or between the 2nd input of the operational amplifier 16 and other reference voltage terminal with switches S3, S4. A switching means 15 connects the input terminals to a common terminal (RF0) for a period Δt after activation of a signal SW.
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公开(公告)号：JPH07283664A
公开(公告)日：1995-10-27
申请号：JP29668694
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO
Abstract: PURPOSE: To obtain a high output dynamic characteristic, a satisfactory gain bandwidth product, and a satisfactory stability with a low voltage power source by constituting input and output circuits of differential types using FETs having low and high thresholds and inversely feeding back them to each other by first and second capacitors. CONSTITUTION: The input circuit consists of a differential stage of transistors TRs M1 and M2, a cascode stage of TRs M3 to M6, and a TR M0, and the output circuit consists of TRs M7A, M7B2, M8A, and M8B, and they are constituted of differential types. Control terminals of output TRs M8A and M8B are connected to nodes A and B and output terminals VOUT+ and VOUT- are connected to nodes C and D through capacitors CcA and CcB to perform mutual inverse feedback. A power VCC is supplied to input and output circuits through current generators of these TRs M0, M7A, and M7B, and MOS TRs having a high threshold are used as TRs M8A and M8B, and MOS TRs having a low threshold are used as TRs M3 to M6. Thus, a high output dynamic characteristic, a satisfactory gain bandwidth product, and a satisfactory stability are obtained with a low voltage power source.
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Patent Agency Ranking
公开(公告)号：DE602005017256D1
公开(公告)日：2009-12-03
申请号：DE602005017256
申请日：2005-06-09
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO , GARIBALDI FEDERICO
IPC: H03M3/04
Abstract: A single-loop differential switched-capacitors Sigma-Delta converter has a three stage double-sampling architecture, a reduced current consumption and is stable even for large input dynamics. The latter characteristic makes it suitable for RF applications. The novel three-stage multi-bit double-sampled architecture of a Sigma-Delta converter has a single-loop architecture, that is all integrators are included in a same feedback loop. This has been made possible by an effective choice of the type of integrators of the converter connected in cascade. Thanks to its innovative architecture, the functioning of the converter is less sensitive to non idealities of the operational amplifiers of the integrators.
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公开(公告)号：IT1319613B1
公开(公告)日：2003-10-20
申请号：ITMI20002806
申请日：2000-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO , STEVENAZZI FABIO , NICOLLINI GERMANO
Abstract: It is described a circuit generating a stable reference voltage with respect to temperature, which circuit is connected between first and second voltage references and comprises at least one current generating circuit adapted to inject a reference current into a resistive element connected between a base terminal of a bipolar transistor and an additional voltage reference. The bipolar transistor is connected between the first and second voltage references and to an output terminal of the generator circuit whereat the stable reference voltage with respect to temperature is. The generator circuit further comprises at least another resistive element, feedback connected between the output terminal of the generator circuit and the base terminal of the bipolar transistor to enable injecting additional current, having reverse dependence on temperature from the reference current, into the resistive element.
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公开(公告)号：DE69920404D1
公开(公告)日：2004-10-28
申请号：DE69920404
申请日：1999-05-14
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , PERNICI SERGIO
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公开(公告)号：DE69325810T2
公开(公告)日：1999-11-18
申请号：DE69325810
申请日：1993-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO
Abstract: High-performance operational transconductance amplifier monolithically integrable with CMOS technology comprising a differential input stage (M1,M2) connected to a pair of cascode stages (M3,M5 and M4,M6) and a differential output stage (M7A,M7B,M8A,M8B). The output stage comprises two output transistors (M8A,M8B) whose command terminals are connected to nodes (A,B) for connection of the input stage and the cascode stages. The output terminals (VOUT+, VOUT-) of the amplifier are connected to intermediate nodes (C,D) of the cascode stages through condensers (CCA,CCB).
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公开(公告)号：DE69325810D1
公开(公告)日：1999-09-02
申请号：DE69325810
申请日：1993-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PERNICI SERGIO
Abstract: High-performance operational transconductance amplifier monolithically integrable with CMOS technology comprising a differential input stage (M1,M2) connected to a pair of cascode stages (M3,M5 and M4,M6) and a differential output stage (M7A,M7B,M8A,M8B). The output stage comprises two output transistors (M8A,M8B) whose command terminals are connected to nodes (A,B) for connection of the input stage and the cascode stages. The output terminals (VOUT+, VOUT-) of the amplifier are connected to intermediate nodes (C,D) of the cascode stages through condensers (CCA,CCB).
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