公开(公告)号：DE69913337T2

公开(公告)日：2004-10-07

申请号：DE69913337

申请日：1999-07-26

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO

IPC: G11C16/12 ,  G11C16/10

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

公开(公告)号：DE69941829D1

公开(公告)日：2010-01-28

申请号：DE69941829

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

IPC: G11C16/04 ,  G11C16/12 ,  G11C16/30

Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

公开(公告)号：DE69913337D1

公开(公告)日：2004-01-15

申请号：DE69913337

申请日：1999-07-26

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO

IPC: G11C16/12 ,  G11C16/10

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

公开(公告)号：DE69932703T2

公开(公告)日：2007-09-06

申请号：DE69932703

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/12

Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

公开(公告)号：DE69932703D1

公开(公告)日：2006-09-21

申请号：DE69932703

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/12

Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

公开(公告)号：DE60119483D1

公开(公告)日：2006-06-14

申请号：DE60119483

申请日：2001-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  GOMIERO ENRICO

IPC: G11C16/08 ,  G11C7/18