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    1.
    发明专利
    未知

    公开(公告)号：DE602004026447D1

    公开(公告)日：2010-05-20

    申请号：DE602004026447

    申请日：2004-09-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDESCHI FERDINANDO ,  PELLIZZER FABIO ,  BENVENUTI AUGUSTO ,  VENDRAME LORIS ,  ZULIANI PAOLA

    IPC: G11C16/02 ,  G11C11/34

    Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

    2.
    发明专利
    未知

    公开(公告)号：DE69932703T2

    公开(公告)日：2007-09-06

    申请号：DE69932703

    申请日：1999-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

    IPC: G11C16/30 ,  G11C16/04 ,  G11C16/12

    Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

    3.
    发明专利
    未知

    公开(公告)号：DE69932703D1

    公开(公告)日：2006-09-21

    申请号：DE69932703

    申请日：1999-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

    IPC: G11C16/30 ,  G11C16/04 ,  G11C16/12

    Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

    MEMOIRE A CHANGEMENT DE PHASE
    7.
    发明专利
    MEMOIRE A CHANGEMENT DE PHASE 未知

    公开(公告)号：FR3065314A1

    公开(公告)日：2018-10-19

    申请号：FR1753345

    申请日：2017-04-18

    Applicant: ST MICROELECTRONICS CROLLES 2 SAS ,  ST MICROELECTRONICS SRL

    Inventor： MORIN PIERRE ,  HAOND MICHEL ,  ZULIANI PAOLA

    IPC: H01L45/00 ,  G11C13/02

    Abstract: L'invention concerne une mémoire à changement de phase comprenant un élément résistif (28) en forme de L, une première partie de l'élément résistif (28) s'étendant entre une couche de matériau à changement de phase (32) et l'extrémité supérieure d'un via conducteur (21), une seconde partie de l'élément résistif (28) reposant au moins partiellement sur l'extrémité supérieure du via conducteur (21), la partie supérieure du via conducteur (21) étant entourée d'un isolant (46) non susceptible de réagir avec l'élément résistif (28).

    8.
    发明专利
    未知

    公开(公告)号：DE69941829D1

    公开(公告)日：2010-01-28

    申请号：DE69941829

    申请日：1999-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

    IPC: G11C16/04 ,  G11C16/12 ,  G11C16/30

    Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

    9.
    发明专利
    未知

    公开(公告)号：DE602005009793D1

    公开(公告)日：2008-10-30

    申请号：DE602005009793

    申请日：2005-01-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZULIANI PAOLA ,  PELLIZZER FABIO ,  BEZ ROBERTO

    IPC: H01L27/24

    Abstract: Phase-change memory device, wherein memory cells (2) are arranged in rows (7) and columns (6) and form a memory array. The memory cells (2) are formed by a selection device (4) of an MOS type and by a phase-change region (3) connected to the selection device. The selection device (4) is formed by a first conductive region (32) and a second conductive region (33), which extend in a substrate (31) of semiconductor material and are spaced from one another via a channel region (34), and by an isolated control region (36) connected to a respective row (7) and overlying the channel region (34). The first conductive region (32) is connected to a connection line (42) extending parallel to the rows, the second conductive region (33) is connected to the phase-change region (46), and the phase-change region is connected to a respective column (6). The first connection line (42) is a metal interconnection line and is connected to the first conductive region (32) via a source-contact region (40) made as point contact and distinct from the first connection line (42).

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