公开(公告)号：JPH05251555A

公开(公告)日：1993-09-28

申请号：JP32069592

申请日：1992-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247

Abstract: PURPOSE: To improve electric characteristics of a final device by reducing a masking process at the time of channel stopper formation by selectively implanting selected conductive ions in a substrate through a specific field insulating region after a semiconductor polysilicon material layer is formed on the substrate. CONSTITUTION: Immediately after a resist layer 5 has been removed, a thick field oxide region 10 is grown, a nitride layer 4 and an oxide layer 3 are removed, and a gate oxide layer 131 is grown. Then the implantation is carried out after a 1st polysilicon layer 14 has been adhered. Then a memory cell region, etc., of the 1st polysilicon layer is exposed by using a resist mask 20, the 1st polysilicon layer 14 on a field oxide region 10 formed on a P-type substrate 1 is exposed, and a channel stopper is formed below it. After the exposed part of the 1st polysilicon layer 14 has been removed, implantation is carried out with high energy to form a P+-type channel stopper 8'.

公开(公告)号：ITMI991680D0

公开(公告)日：1999-07-28

申请号：ITMI991680

申请日：1999-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： LAURIN ENRICO ,  BORDOGNA MATTEO ,  BERNARDI ORESTE

IPC: H01L31/0216

公开(公告)号：IT1313260B1

公开(公告)日：2002-07-17

申请号：ITMI991680

申请日：1999-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： LAURIN ENRICO ,  BORDOGNA MATTEO ,  BERNARDI ORESTE

IPC: H01L31/0216

公开(公告)号：ITMI991680A1

公开(公告)日：2001-01-29

申请号：ITMI991680

申请日：1999-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： LAURIN ENRICO ,  BORDOGNA MATTEO ,  BERNARDI ORESTE

IPC: H01L31/0216

公开(公告)号：IT1250233B

公开(公告)日：1995-04-03

申请号：ITTO910929

申请日：1991-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H03K

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.

公开(公告)号：DE69231484T2

公开(公告)日：2001-02-08

申请号：DE69231484

申请日：1992-11-02

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/82

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.

公开(公告)号：DE69231484D1

公开(公告)日：2000-11-02

申请号：DE69231484

申请日：1992-11-02

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/82

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.