公开(公告)号：JPH05251555A

公开(公告)日：1993-09-28

申请号：JP32069592

申请日：1992-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247

Abstract: PURPOSE: To improve electric characteristics of a final device by reducing a masking process at the time of channel stopper formation by selectively implanting selected conductive ions in a substrate through a specific field insulating region after a semiconductor polysilicon material layer is formed on the substrate. CONSTITUTION: Immediately after a resist layer 5 has been removed, a thick field oxide region 10 is grown, a nitride layer 4 and an oxide layer 3 are removed, and a gate oxide layer 131 is grown. Then the implantation is carried out after a 1st polysilicon layer 14 has been adhered. Then a memory cell region, etc., of the 1st polysilicon layer is exposed by using a resist mask 20, the 1st polysilicon layer 14 on a field oxide region 10 formed on a P-type substrate 1 is exposed, and a channel stopper is formed below it. After the exposed part of the 1st polysilicon layer 14 has been removed, implantation is carried out with high energy to form a P+-type channel stopper 8'.

公开(公告)号：JP2003163294A

公开(公告)日：2003-06-06

申请号：JP2002294069

申请日：2002-10-07

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPRARA PAOLO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To simplify the step of manufacturing a double charge storage location memory cell. SOLUTION: A dielectric stack 120 is disposed over the entire upper side surface of a structure. A contact opening 121 is formed in the dielectric layer 120 lowered to the surface of a bit line diffused part 115 of the specified region at the outside of the memory cell sub-array. Metal bit lines 123A, 123B are specified to cross a word line 119 on the bit line diffused part 115 so as to bring into contact with the position corresponding to the specified region by a normal contact forming technique and a metallization technique. The metal bit line restricts the voltage drop along the bit line diffused part 115. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001168303A

公开(公告)日：2001-06-22

申请号：JP24214498

申请日：1998-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

IPC: G11C16/04 ,  G11C8/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a new method of manufacturing an electronic memory device which is integrated on a semiconductor containing a virtual ground cell matrix. SOLUTION: A matrix is formed on a semiconductor substrate 10 as it is provided with continuous bit lines 7 which extend as discrete parallel stripes traversing a substrate 10. The matrix contains a circuit part C' for selective transistors 20, and a decoder equipped with a P-channel and an N-channel MOS transistor and an address circuits A and B are built in a memory device. A process in which an N well 11 where the P-channel transistor is housed is formed on a part A of the substrate, and another process in which the active regions of all transistors are specified by a screen mask 33 and an isolation layer 13 is grown through the intermediary of an opening provided to the mask 33, are at least provided. The active region specifying mask 33 is not opened on the matrix region C" of the memory cell.

公开(公告)号：JPH10335478A

公开(公告)日：1998-12-18

申请号：JP13185698

申请日：1998-05-14

Applicant: ST MICROELECTRONICS SRL

Inventor： STUCCHI ELENA ,  DAFFRA STEFANO ,  CEREDA MANLIO SERGIO

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/329 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit without making a manufacturing process complex and without increasing the number of generated defects. SOLUTION: An insulation layer for constituting a polycrystal Si part that prescribes an opening for forming the gate electrode and the resistor of a MOSTr, a P ion injection 27 with a low amount of concentration for forming a pair of n-type conductive parts 19 and 20 at both sides of a gate thin line part (electrode) 14, and the injection mask of polycrystalline Si including an n-type conductive resistance part 21 due to an opening are formed. Then, a resist insulation layer is formed on an entire structure, an insulation layer is subjected to anisotropic etching so that the region of a substrate without Si mask can be exposed, and the residue of an insulation material remains along the edge part of the gate electrode. For compensating for the elimination of a surface layer from a resistance part due to etching, a dosage amount where the resistance part 21 becomes a scheduled resistance value are subjected to second ion implantation by energy without any substrate mask and without changing resistance values in source and drain of MOSTr.

公开(公告)号：JPH07201848A

公开(公告)日：1995-08-04

申请号：JP29764794

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  DAFFRA STEFANO ,  STUCCHI ELENA

IPC: H01L21/318 ,  H01L21/314 ,  H01L27/115

Abstract: PURPOSE: To reduce the extent of complexity of processes, to provide superior reliability, and to lower the cost of a device instituted by this method. CONSTITUTION: By an inactivating method which uses a silicon oxide nitride, a circuit structure is converted with a 1st layer 8 of at least a dielectric substance before its layer is formed, and a 2nd layer 9 of a dielectric substance is laminated on it. These layers 8 and 9 are thick enough to planarize the surface of the top part. Further, this is usable together with an inactivating method which features flattening by the formation of the same dielectric layer by a base shape and does not use oxide nitride 10.

公开(公告)号：DE69732838D1

公开(公告)日：2005-04-28

申请号：DE69732838

申请日：1997-07-16

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO

IPC: H01L21/8247 ,  H01L23/528 ,  H01L27/105 ,  H01L27/115

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD), said defining the second strips (17) providing for selectively etching the first and second layers of conductive material (9,11) outside the memory cell array area by means of a first mask (MASK1), and said defining the first strips (22) providing for selectively etching the second layer of conductive material (11), the layer of insulating material (10) and the first layer of conductive material (9) inside the memory cell array area by means of a second mask (MASK2). The first and second masks (MASK1,MASK2) overlap in a boundary region around the memory cell array area, so that the first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

公开(公告)号：DE69732293D1

公开(公告)日：2005-02-24

申请号：DE69732293

申请日：1997-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIO VALERIO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

公开(公告)号：DE69631029D1

公开(公告)日：2004-01-22

申请号：DE69631029

申请日：1996-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  GINAMI GIANCARLO ,  DAFFRA STEFANO ,  RAVAGLIA ANDREA ,  CEREDA MANLIO SERGIO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, which comprises the following steps: -- forming field oxide regions (14) and drain active area regions (15) on a substrate (1); -- forming word lines (16) on the field oxide regions (14); -- depositing oxide to form oxide wings (13) that are adjacent to the word lines (16); characterized in that it comprises the following additional steps: -- opening, by masking (20), source regions (18) and the drain active area regions (15), keeping the field oxide regions (14) that separate one memory cell from the other, inside the memory, covered with resist; and -- removing field oxide (14) in the source regions (18) and removing oxide wings (13) from both sides of the word lines (16).

公开(公告)号：DE69921086D1

公开(公告)日：2004-11-18

申请号：DE69921086

申请日：1999-02-26

Applicant: ST MICROELECTRONICS SRL ,  WAFERSCALE INTEGRATION INC

Inventor： POZZONI PIERANTONIO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO ,  IRANI RUSTON

IPC: H01L21/8247

公开(公告)号：IT1250233B

公开(公告)日：1995-04-03

申请号：ITTO910929

申请日：1991-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO ,  LAURIN ENRICO ,  RAVAGLIA ANDREA

IPC: H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H03K

Abstract: A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.