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    1.
    发明专利
    未知

    公开(公告)号：DE60211846D1

    公开(公告)日：2006-07-06

    申请号：DE60211846

    申请日：2002-03-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LO IACONO DANIELE ,  MESSINA ETTORE ,  AVELLONE GIUSEPPE ,  GALLUZZO AGOSTINO

    IPC: H04J13/00 ,  H04J13/10

    Abstract: In order to generate the main scrambling code of order N and the secondary scrambling code of order K within the set identified by the primary scrambling code of order N, a first m-sequence and a second m-sequence are generated using Fibonacci linear feedback shift registers (LFSRs). Then said first m-sequence and said second m-sequence are modulo-2 added so as to form the I branch of said primary scrambling code. A first T-bit masking word and a second T-bit masking word of rank 0 (X0-MASK, Y0-MASK) are generated that correspond to the polynomial time shifts (X0 (D), Y0 (D)), and the intermediate taps of the X and y registers respectively chosen by means of said masking words (X0-MASK, Y0-MASK) are modulo-2 added so as to generate a third sequence and a fourth sequence which are modulo-2 added together to form the Q branch of said primary scrambling code. With the choice, starting from the least significant Kmax bits of the register X, of the K-th intermediate tap corresponding to the secondary scrambling code of order K within said set identified by the primary scrambling code of order N, a fifth sequence is generated, which, modulo-2 added to said second sequence, forms the I branch of said secondary scrambling code. By modulo-2 summing the intermediate taps of the register X masked by means of the aforesaid first masking word of rank N (XN-MASK), a sixth sequence is generated, which, modulo-2 added to the aforesaid fourth sequence, forms the Q branch of the secondary scrambling code.

    2.
    发明专利
    未知

    公开(公告)号：DE602006009596D1

    公开(公告)日：2009-11-19

    申请号：DE602006009596

    申请日：2006-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LO IACONO DANIELE

    IPC: G06F9/38

    Abstract: A data processor unit (180), including at least two operation-execution units (PU1,..., PUn), each operation-execution unit being adapted to: receive input data (DX1,..DXn, DY1,..Dyn, DZ1,..DZn); perform a respective operation on the input data; and outputting output data (DO1,...,DOn) resulting from said input data after applying said operation, the data processor unit further including: a data storage unit ( 220 ) including at least two individually-accessible memory devices (B1,.., Bm) adapted to store data; a programmable controller ( 205 ) adapted to be programmed so as to execute a selected program; a first data routing circuit arrangement ( 225 ) adapted to receive data from the at least two memory devices, from the programmable controller and from a second data routing circuit arrangement ( 235 ), and for selectively routing selected ones among the received data to the input of the operation-execution units; said second data routing circuit arrangement being adapted to receive the output data outputted by the operation-execution units and to selectively route the output data to the at least two memory devices, to the programmable controller, and to the first data routing circuit arrangement; wherein the programmable controller is operatively coupled to the at least two operation-execution units, to the first and second data routing circuit arrangements, and to the at least two memory devices for controlling the operation thereof.

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