公开(公告)号：JP2000059224A

公开(公告)日：2000-02-25

申请号：JP9750699

申请日：1999-04-05

Applicant: ST MICROELECTRONICS SRL

Inventor： BIANCHESSI MARCO ,  DALLE FESTE SANDRO ,  SERINA NADIA ,  ANGELICI MARCO ,  OSNATO FABIO

IPC: H03M1/08 ,  H03M3/02

Abstract: PROBLEM TO BE SOLVED: To provide a sigma delta modulator securing the stability of a system and simplifying constitution. SOLUTION: The modulator is provided with at least two integration stages A, a comparator generating a signal at a logical level +1 in the case that an inputted signal is positive and a signal of a logical value -1 in the case that the inputted signal is negative without regard to its absolute value, and an adding means adding a feedback signal filtered by at least one low-pass filter B to a signal to be outputted to the last of the stage A. In addition, the modulator is provided with a second comparator which is commonly connected with the output end of the first comparator and outputs a logical signal being a positive value in the case that an inputted signal is positive and being a negative value in the case that the inputted signal is negative, the logical signal is increased in the case that the input signal exceeds one of increasing values or a prescribed threshold larger than it and an outputted logical signal is provided to the filter B.

公开(公告)号：DE69809710D1

公开(公告)日：2003-01-09

申请号：DE69809710

申请日：1998-04-03

Applicant: ST MICROELECTRONICS SRL

Inventor： BIANCHESSI MARCO ,  DALLE FESTE SANDRO ,  SERINA NADIA ,  ANGELICI MARCO ,  OSNATO FABIO

IPC: H03M1/08 ,  H03M3/02 ,  H03M3/00

Abstract: A sigma-delta modulator of second or higher order, comprising two or more integrating stages (A), a comparator (Comp) in cascade to the integration stages, generating a signal of logic level +1 when the input signal is positive or of logic value -1 when the input signal is negative, regardless of its absolute value, a feedback line comprising at least a low-pass filter (B) and adder means adding a feedback signal, filtered by the low-pass filter (B) to the signal output by the last of the integrating stages (A), further comprises a second comparator (Comp2) having an input connected in common to the input of the first comparator (Comp) and outputting a logic signal of positive value when the input signal is positive and of negative value when the input signal is negative, but of increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value and the output logic signal being fed to the input of the low-pass filter (B).

公开(公告)号：DE60136611D1

公开(公告)日：2009-01-02

申请号：DE60136611

申请日：2001-05-10

Applicant: ST MICROELECTRONICS SRL

Inventor： FERRARI MARCO ,  SITI MASSIMILIANO ,  VALLE STEFANO ,  OSNATO FABIO ,  SCALISE FABIO

IPC: H03M13/27 ,  H03M13/00 ,  H03M13/29

Abstract: A method is described for designing a new prunable S-random interleaver (I) class to be used as a constituent part of turbo codes (C1, C2). With respect to previously proposed solutions the method has the advantage of being prunable to different block sizes while exhibiting at the same time, for any considered block size, performance comparable with the optimized "ad hoc" S-random interleavers. Another advantage is that, as for every S-random interleaver, the design rules are independent of the constituent codes and of the puncturing rate applied to the turbo code. Therefore, these interleavers potentially can find applications in any turbo code scheme (C1, C2) that requires interleaver size flexibility and code rate versatility, thanks to the advantage of requiring a single law storage (i.e. one ROM storage instead of several ROMs) from which all the others are obtained by pruning, without compromising the overall error rate performance.

公开(公告)号：IT201900006609A1

公开(公告)日：2020-11-07

申请号：IT201900006609

申请日：2019-05-07

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASONI ALESSANDRO ,  LO IACONO DANIELE ,  OSNATO FABIO

IPC: H04L20060101

公开(公告)号：DE69809710T2

公开(公告)日：2003-09-18

申请号：DE69809710

申请日：1998-04-03

Applicant: ST MICROELECTRONICS SRL

Inventor： BIANCHESSI MARCO ,  DALLE FESTE SANDRO ,  SERINA NADIA ,  ANGELICI MARCO ,  OSNATO FABIO

IPC: H03M1/08 ,  H03M3/02 ,  H03M3/00

Abstract: A sigma-delta modulator of second or higher order, comprising two or more integrating stages (A), a comparator (Comp) in cascade to the integration stages, generating a signal of logic level +1 when the input signal is positive or of logic value -1 when the input signal is negative, regardless of its absolute value, a feedback line comprising at least a low-pass filter (B) and adder means adding a feedback signal, filtered by the low-pass filter (B) to the signal output by the last of the integrating stages (A), further comprises a second comparator (Comp2) having an input connected in common to the input of the first comparator (Comp) and outputting a logic signal of positive value when the input signal is positive and of negative value when the input signal is negative, but of increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value and the output logic signal being fed to the input of the low-pass filter (B).