公开(公告)号：ITMI991475D0

公开(公告)日：1999-07-02

申请号：ITMI991475

申请日：1999-07-02

Applicant: ST MICROELECTRONICS SRL

Inventor： MULATTI JACOPO ,  MACCARONE MARCO

IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30

Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.

公开(公告)号：ITMI991474D0

公开(公告)日：1999-07-02

申请号：ITMI991474

申请日：1999-07-02

Applicant: ST MICROELECTRONICS SRL

Inventor： MULATTI JACOPO ,  MACCARONE MARCO

IPC: G11C16/30 ,  G11C29/02 ,  G11C29/50

公开(公告)号：ITMI991475A1

公开(公告)日：2001-01-02

申请号：ITMI991475

申请日：1999-07-02

Applicant: ST MICROELECTRONICS SRL

Inventor： MULATTI JACOPO ,  MACCARONE MARCO

IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30

Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.

公开(公告)号：ITMI991474A1

公开(公告)日：2001-01-02

申请号：ITMI991474

申请日：1999-07-02

Applicant: ST MICROELECTRONICS SRL

Inventor： MULATTI JACOPO ,  MACCARONE MARCO

IPC: G11C16/30 ,  G11C29/02 ,  G11C29/50