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    NEGATIVE ELECTRIC CHARGE PUMP
    1.
    发明专利
    NEGATIVE ELECTRIC CHARGE PUMP 失效

    公开(公告)号：JPH10303311A

    公开(公告)日：1998-11-13

    申请号：JP30446697

    申请日：1997-11-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  MULATTI JACOPO ,  BRANCHETTI MAURIZIO

    IPC: H01L21/8247 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To improve efficiency of an electric charge pump by providing each stage of the second group with a joint diode comprising a first electrode connected to an input terminal and a second electrode connected to an output terminal and a second capacitor comprising a first polar plate connected to an output terminal and a second polar plate driven by a digital signal. SOLUTION: Between an output terminal O and an input terminal of an electric charge pump connected to a ground, four stages S1, S2, S3', and S4' are connected in series. Then, with a first group stage as S1 and S2 while a second group stage S3' and S4', a joint diode D comprising a first electrode connected to an input terminal of the second group S3' and a second electrode connected to an output terminal of the S3' is provided, and a second capacitor CL' comprising a first polar plate connected to the output terminal of the S3' and S4' and a second polar plate driven by respective phase signals B' and D' is provided.

    OUTPUT CIRCUIT FOR INTEGRATED CIRCUIT
    2.
    发明专利
    OUTPUT CIRCUIT FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11195715A

    公开(公告)日：1999-07-21

    申请号：JP29938198

    申请日：1998-10-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MULATTI JACOPO ,  ZANARDI STEFANO ,  GOLLA CARLA MARIA ,  CONCI ARMANDO

    IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175

    Abstract: PROBLEM TO BE SOLVED: To reduce the effects of noise exerted to an input stage and internal circuit of an integrated circuit by an output stage of the integrated circuit. SOLUTION: An output stage for an integrated circuit is provided with a first transistor means P2 and a second transistor means N2, serially connected between a first external voltage Vcc and a second external voltage Gnd on the outside of the integrated circuit 100 respectively, through a first and a second electric connection means L2 and L4. The first transistor means P2 transmits the first external voltage Vcc to an output line 5 of the integrated circuit, and the second transistor means N2 transmits the second external voltage Gnd to the output line 5 of the integrated circuit. The second transistor means N2 is formed inside a first well 130 of a first conductivity type provided inside a second well 140 of a second conductivity type formed inside a substrate 7 of the first conductivity type. The second well 140 of the second conductive type is connected through a third electric connection means L21 which is different from the first electric connection means L2 to the first external voltage Vcc.

    Electrostatic discharge protective network
    3.
    发明专利
    Electrostatic discharge protective network 审中-公开
    静电放电保护网络

    公开(公告)号：JPH11274319A

    公开(公告)日：1999-10-08

    申请号：JP37471898

    申请日：1998-12-28

    Applicant: St Microelectronics Srl ,  エスティマイクロエレクトロニクス・ソチエタ・ア・レスポンサビリタ・リミタータ

    Inventor： COLOMBO PAOLO ,  MULATTI JACOPO ,  CAMPARDO GIOVANNI ,  MACCARRONE MARCO ,  ANNUNZIATA ROBERTO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/0259 ,  H01L27/0251

    Abstract: PROBLEM TO BE SOLVED: To provide an electrostatic discharge(ESD) protective network, which has such structural and functional features that meet the nonsensitive requirements of a substrate for noise and accordingly, can isolate various circuit blocks from noise or disturbance. SOLUTION: An ESD protective network incorporates first ESD protective parts 14 for the input stage of a circuit structure, second ESD protective parts 5 for the output stage of the circuit structure, at least one ESD protective parts B0 between a primary power source Vcc and a primary ground GND, and at least one EDGE protective parts B between a secondary power source Vcc- IO and a secondary ground GND- IO, and the first and second protective parts 15 and 5 commonly use the input-output terminal 20 of an integrated circuit structure.

    Abstract translation: 要解决的问题：提供一种静电放电（ESD）保护网络，其具有满足基板对噪声的不敏感要求的结构和功能特征，因此可以将各种电路块与噪声或干扰隔离开来。 解决方案：ESD保护网络包括用于电路结构的输入级的第一ESD保护部件14，用于电路结构的输出级的第二ESD保护部件5，主电源Vcc和 主接地GND以及次级电源Vcc-IO和次级地GND-IO之间的至少一个EDGE保护部分B，并且第一和第二保护部分15和5通常使用集成电路的输入 - 输出端子20 结构体。

    5.
    发明专利
    未知

    公开(公告)号：DE69733603D1

    公开(公告)日：2005-07-28

    申请号：DE69733603

    申请日：1997-01-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  MULATTI JACOPO ,  BRANCHETTI MAURIZIO

    IPC: H02M3/07

    Abstract: A negative charge pump circuit comprises a plurality of charge pump stages (S1'-S4') connected in series to each other. Each stage has a stage input terminal (SI) and a stage output terminal (SO). A first stage (S1') has the stage input terminal (SI) connected to a reference voltage, a final stage (S4') has the stage output terminal (SO) operatively connected to an output terminal (O) of the charge pump at which a negative voltage is developed; intermediate stages (S2' ,S3') have the respective stage input terminal (SI) connected to the stage output terminal (SO) of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage (S1'-S4') comprises a first N-channel MOSFET (M1') with a first electrode connected to the stage input terminal (SI) and a second electrode connected to the stage output terminal (SO), a second N-channel MOSFET (M2') with a first electrode connected to the stage output terminal (SO) and a second electrode connected to a gate electrode of the first N-channel MOSFET (M1'), a boost capacitor (CP) with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal (A',C') switching between the reference voltage and a positive voltage supply (VDD), and a second capacitor (CL) with one terminal connected to the charge pump stage output terminal (SO) and a second terminal connected to a respective second digital signal (B',D') switching between the reference voltage and the voltage supply (VDD). A gate electrode of the second N-channel MOSFET (M2') is connected, in the first stage (S1'), to a third digital signal (D') switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal (SI).

    7.
    发明专利
    未知

    公开(公告)号：ITMI991475D0

    公开(公告)日：1999-07-02

    申请号：ITMI991475

    申请日：1999-07-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MULATTI JACOPO ,  MACCARONE MARCO

    IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30

    Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.

    8.
    发明专利
    未知

    公开(公告)号：DE602005011628D1

    公开(公告)日：2009-01-22

    申请号：DE602005011628

    申请日：2005-10-10

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS ASIA ,  ST MICROELECTRONICS SRL

    Inventor： JEONG KUHONG ,  LEE HYUNGSANG ,  MULATTI JACOPO

    IPC: G11C16/34

    Abstract: A method of programming cells of a destination page of a nonvolatile memory and verifying whether logic values stored in programmed cells of a source page of the same memory have been correctly copied into corresponding cells of the destination page, exploits both the fast but inadequate-at-times Global Verify operation and, if the Global Verify operation fails for a certain number of attempts, the Byte-by-byte Verify operation, which is slower but accurate.

    9.
    发明专利
    未知

    公开(公告)号：DE60130774T2

    公开(公告)日：2008-07-17

    申请号：DE60130774

    申请日：2001-10-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LOMAZZI GUIDO ,  MULATTI JACOPO ,  SURICO STEFANO

    IPC: G11C16/10

    Abstract: The programming method includes the following steps: sequentially receiving (23, 27) a plurality of data words; temporarily storing (24, 29) each data word after its reception; and simultaneously writing (31, 35) in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments (25) an address counter and sends a "ready" signal (26). Upon reception of each new data word (27), the memory verifies whether the address associated thereto is in the same sector as the initial data word (28) and whether n data words have already been stored (30). If the sector is different, blind-programming step is terminated (35, 36) and the verifying is carried out (37); if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array (31), updates the address counter (25), and then sends the "ready" signal (26).

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