公开(公告)号：DE69930238D1

公开(公告)日：2006-05-04

申请号：DE69930238

申请日：1999-06-17

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OHBA ,  CARRERA MARCELLO

IPC: G11C16/06 ,  G11C16/12 ,  G11C8/00 ,  G11C8/08 ,  G11C11/56 ,  H03K19/173

Abstract: The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (VCC) and a ground voltage (VGND) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (VPC), in turn switching at least between the supply voltage (VCC) and a programming voltage (VPP) higher than the supply voltage (VCC), and a second operating voltage (VNEG), in turn switching at least between the ground voltage (VGND) and an erase voltage (VERN) lower than the ground voltage (VGND). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (VPC, VNEG) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).