公开(公告)号：JP2001229691A

公开(公告)日：2001-08-24

申请号：JP2000374346

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MANSTRETTA ALESSANDRO ,  MICHELONI RINO ,  PIERIN ANDREA ,  YERO EMILIO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory device having row redundancy being freely constituted in which correcting capability of architecture can be reconstituted for each chip. SOLUTION: This device comprises a row decoding circuit 12 and a column decoding circuit 13, a circuit reading out stored data in a memory cell and changing it, a memory matrix 14 which can store a fault row address, and a control circuit. The device also comprises a circuit comparing a fault row address stored in the memory matrix 14 with a selected row address in order to recognize a selected row address ADr and perform relieving selection of a fault row and selection of a corresponding redundant cell row at the time of recognizing validness, and configuration register comprising a matrix of a non-volatile memory cell and a control circuit.

公开(公告)号：JP2001035179A

公开(公告)日：2001-02-09

申请号：JP2000187530

申请日：2000-06-19

Applicant: ST MICROELECTRONICS SRL ,  MITSUBISHI ELECTRIC CORP

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OBA ATSUSHI ,  CARRERA MARCELLO

IPC: G11C16/06 ,  G11C8/08 ,  G11C11/56 ,  G11C16/12 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To enable biasing selectively a word line by positive or negative voltage with a simple method for a circuit. SOLUTION: This decoder is provided in a first reference line 42, a second reference line 44, a third reference line 46 and a word line WL respectively, and the decoder is provided with a bias circuit 54 receiving a row selecting signal SR at an input and transmitting a bias signal R for each word line WL at an output, an output driver circuit 60 supplying the bias signal R from each bias circuit 54 to an output 96, and a level conversion circuit 58 receiving the row selecting signal SR at an input and supplying a control signal CM to an output 84 for each driver circuit 60.

公开(公告)号：JP2002117686A

公开(公告)日：2002-04-19

申请号：JP2001287008

申请日：2001-09-20

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To realize a memory device which can read out information having high speed and high reliability, in some parts of a memory and having high information storage density, in other parts of the memory. SOLUTION: A multi-level memory device has a memory section (multilevel array), including cells being programmable with the prescribed number of level being larger than 2 and a memory section (bilevel array), including cells being programmable with the number of level of 2. The multilevel array is used for storing high density data, in which read speed is not essential such as storing an operation code of a system, including a memory device. The bilevel array is used for storing data required to have high speed and reliability, such as BIOS of a personal computer and data stored in a cache memory, in which the read-out speed is essential such as, storing an operation code of a system, including a memory device. A circuit part, being exclusive for all the functions required for programming, writing of test instructions, and operation of a memory device is common to both arrays.

公开(公告)号：JP2000235799A

公开(公告)日：2000-08-29

申请号：JP2000034209

申请日：2000-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02

Abstract: PROBLEM TO BE SOLVED: To read out a multi-level cell quickly and reliably. SOLUTION: A multi-level memory 50 stores words formed by plural binary sub-words in plural cells 63a, each cell has a threshold value. Cells are arranged in rows and columns, grouped to plural sectors 56 divided in a block 57, selected through a global row decoder 51, a global column decoder 54, and plural local row decoder 58. These decoders supply simultaneously ramp voltage VR to a bias terminal of selected cell. Threshold value read-out comparators 72a, 72b are connected to the selected cell, when ramp voltage reaches a threshold value of the selected cell, a threshold value achievement signal is generated. Switch means 65a... are arranged between a global word line 52 and local word lines 59a..., 60a..., opening of the switch means is controlled individually by a threshold value achievement signal, thereby, a local word line is kept to respective threshold voltage of each selected cell after release.

公开(公告)号：JPH11219590A

公开(公告)日：1999-08-10

申请号：JP31506698

申请日：1998-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  ZAMMATTIO MATTEO ,  FERRARIO DONATO

IPC: G11C11/41 ,  G11C8/18

Abstract: PROBLEM TO BE SOLVED: To provide the method and circuit for adjusting the duration time of an ATD signal pulse which have respectively a functional feature and a structural feature capable of eliminating defects accompanying possible solution by conventional technology. SOLUTION: In this method and circuit for adjusting a pulse synchronizing signal ATD about the reading phase of a memory cell in a semiconductor integrated electronic memory device, a pulse signal ATD is generated in accordance with detecting variation of at least one logic state of plural address input terminals of a memory cell, and an equalizing signal SAEQ for a sense amplifier is also generated. When row voltage reaches the prescribed value being sufficient for realizing highly reliable reading by row voltage, the SAEQ pulse is interrupted (STOP). It is profitable that the interruption of the pulse is caused by the logic signal STOP activated in accordance with exceeding the prescribed voltage value during over-boosting phase of a row of an addressed memory.

公开(公告)号：JP2001135100A

公开(公告)日：2001-05-18

申请号：JP2000272586

申请日：2000-09-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory device in which complete test of a word line can be performed with a low cost. SOLUTION: The non-volatile memory device integrates a memory cell array 2, a voltage generating circuit REG supplying operation voltage Vr to be adjusted to a ward line LWL1, and short circuit detecting circuit 10 in the same chip 100. The short circuit detecting circuit 10 detects output current IM1 of the voltage generating circuit REG for biasing a cell 3 of the selected word line LWL1. The output current IM1 is made a first value IM1' when short circuit is not caused, and it is made a second value IM1" when short circuit is caused between the selected word line LWL1 and adjacent word lines LWL0- LWLn. The short circuit detecting circuit 10 compares output current IM1 of the voltage generating circuit REG with the reference value Iref, and generates a short circuit digital signal Vo indicating whether short circuit is caused at an output or not.

公开(公告)号：JP2001057097A

公开(公告)日：2001-02-27

申请号：JP2000227650

申请日：2000-07-27

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  SACCO ANDREA ,  PICCA MASSIMILIANO

IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10

Abstract: PROBLEM TO BE SOLVED: To obtain a single power voltage type non-volatile storage device having a hierarchical column decoder in which the bias time of a word line at the level of staircase voltage can be shortened. SOLUTION: This storage device 10 has a memory cell array 2 having structure of a form provided with global word lines 4 and local word lines 6, a global column decoding means 8 for addressing the global word lines 4, a local column decoding means 12 for addressing the local word lines 6, a global power supply means 22 for supplying power to the global column decoding means 8, and a local power supply means 24 for supplying power to a local column decoding means 12.

公开(公告)号：JP2001028197A

公开(公告)日：2001-01-30

申请号：JP2000196290

申请日：2000-06-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12

Abstract: PROBLEM TO BE SOLVED: To provide bias to a plurality of memory sectors in a memory element by bulk of a smaller region in a non-volatile memory element of especially a flash type and providing method for bias in a memory element. SOLUTION: A memory element 21 having a plurality of memory sectors 15 each sector of which includes a plurality of memory cells 1 is provided with a hierarchical sector decoding means. One group out of a plurality of groups of bias lines 28-32 is provided to each sector row, and is extended in parallel to a sector row. Each of a plurality of sector switching stages 35 is connected between a corresponding memory sector and a group corresponding to a bias line. A sector switching stage connected to memory sectors arranged in the same sector column is controlled by the same control signals S0, S1 supplied to a control line 40 extending in parallel to a sector column.

公开(公告)号：JP2000357396A

公开(公告)日：2000-12-26

申请号：JP2000139757

申请日：2000-05-12

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MANSTRETTA ALESSANDRO ,  MICHELONI RINO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory having a row redundancy function in which an access time for a memory word is drastically shortened. SOLUTION: In a non-volatile memory device having a memory cell in which rows and columns are arranged and being provided with at least one sector 100 of a matrix cell, a row decoder D and a column decoder decoding an address signal and activating rows and columns respectively, and at least one sector 110 of a redundancy cell, and being able to replace a row of a sector of a matrix cell by a row of a sector of the redundancy cell, the device is provided with a local column decoder J for a sector 100 of a matrix cell and a local column decoder L for a sector 110 of the redundancy cell. Local column decoders L for a matrix cell and for the redundancy cell are controlled by the outside signal so that rows of the sector 110 of the redundancy cell and rows of the sector 100 of a matrix cell are simultaneously activated.

公开(公告)号：JP2002319293A

公开(公告)日：2002-10-31

申请号：JP2002107937

申请日：2002-04-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GREGORI STEFANO ,  MICHELONI RINO ,  PIERIN ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/12

Abstract: PROBLEM TO BE SOLVED: To realize a method for speedily and highly precisely programming a memory cell. SOLUTION: In the method for programming a non-volatile memory cell 1, at least first and second programming pulse trains F1, F2 having pulse width increasing in stages are applied continuously to a control terminal 2 of the memory cell 1, but amplitude increment between a pulse in the first programming train F1 and the next one is made larger than the amplitude increment between a pulse in the second programming train F2 and the next one. Advantageously, third programming pulse trains F0, F3, having pulse width which increases in stages, are applied to the control terminal 2 of the memory cell 1 before the first programming pulse train F1, but amplitude increment between a pulse and the next one is made smaller than the amplitude increment in the first programming train F1, and is substantially equal to the amplitude increment in the second programming train F2 or larger than the amplitude increment in the first programming train F1.