3.
    发明专利
    未知

    公开(公告)号:DE69819677T2

    公开(公告)日:2004-09-30

    申请号:DE69819677

    申请日:1998-02-19

    Abstract: A circuit for switching a capacitor (C) in an exclusive manner, on the selected one of a plurality of integrated amplifiers (A1, A2, ... AN) comprises a first current generator (IB) connected between a first supply node (VCC) and a first node of the circuit (H), a second current generator (IC) connected between a second supply node (GND) and a second node (L) of the circuit, electrically in parallel to the capacitor (C), an array of switches (S1, S2, ..., SN) of the same number of the integrated amplifiers, exclusively switcheable on, each connecting a directly biased diode (D1, D2, ..., DN) between the first node (H) and the second node (L), each integrated amplifier having a supply node coupled to the connecting node between a respective diode and a respective connecting switch of said array.

    4.
    发明专利
    未知

    公开(公告)号:ITMI982076A1

    公开(公告)日:2000-03-27

    申请号:ITMI982076

    申请日:1998-09-25

    Abstract: A current mirror circuit is provided with recovery having high output impedance. The current mirror includes a differential stage having a pair of transistors, and a voltage feedback loop which is stabilized and closed on a first one of the transistors of the differential stage. A second one of the transistors of the differential stage is connected, by its base terminal, to the collector terminal of an output transistor and, by its collector terminal, to the supply voltage. Moreover, the circuit includes a positive feedback loop which has the second transistor of the differential stage and the output transistor. A low-impedance circuit branch is connected to the base terminal of the second transistor of the differential stage and to the collector terminal of the output transistor.

    8.
    发明专利
    未知

    公开(公告)号:DE602004026841D1

    公开(公告)日:2010-06-10

    申请号:DE602004026841

    申请日:2004-05-31

    Abstract: A prescaling stage is described of the type comprising at least one bistable circuit in turn including respective master and slave portions (2, 3) inserted between a first and a second voltage reference (Vcc, GND) and feedback connected to each other. Each portion is provided with at least one differential stage (4, 5) supplied by the first voltage reference (Vcc) and connected, by means of a transistor stage (52, 53), to the second voltage reference (GND), as well as a differential pair (6, 7) of cross-coupled transistors, supplied by output terminals of the differential stage (4, 5) and connected, by means of the transistor stage (52, 53), to the second voltage reference (GND). Advantageously according to the invention, each master and slave portion (2, 3) comprises at least one degeneracy capacity (C2, C3) inserted in correspondence with respective terminals of the transistors of the differential pair (6, 7).

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