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    1.
    发明专利
    未知

    公开(公告)号：DE602004012255T2

    公开(公告)日：2009-03-19

    申请号：DE602004012255

    申请日：2004-08-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PELLERITI ROBERTO

    IPC: H03F1/56

    Abstract: The following invention refers to a low noise amplifier comprising at least one first circuit block (1, Q1-Q4, Q11-Q12) capable of amplifying a first voltage signal (Vin, V(INP)-V(INN)) in input to the amplifier. The first circuit block (1, Q1-Q4, Q11-Q12) has at least one first terminal coupled to a first supply voltage (Vee) by means of first variable resistor means (RE,2) and at least one second terminal coupled with a second supply voltage (Vcc) by means of at least one resistor (Rc, Rc1, Rc2). The at least one second terminal is coupled to the at least one output terminal of the amplifier (OUT, OUTP-OUTN) and said input voltage signal (Vin, V(INP)-V(INN)) is applied to the at least one further terminal (IN, INP-INN) of the first circuit block. The amplifier comprises a feedback network (RF, RF1, RF2) coupled to the output terminal (OUT, OUTP-OUTN) and to the at least one further terminal (IN, INP-INN) of the first circuit block. The amplifier comprises second circuit means (3) placed between the second supply voltage (Vcc) and the at least one further terminal (IN, INP-INN) of the first circuit block and adapted to compensate the variations in value of said first variable resistor means (RE,2) to ensure a substantially constant input resistance (R in ) of the amplifier.

    2.
    发明专利
    未知

    公开(公告)号：DE602004012255D1

    公开(公告)日：2008-04-17

    申请号：DE602004012255

    申请日：2004-08-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PELLERITI ROBERTO

    IPC: H03F1/56

    Abstract: The following invention refers to a low noise amplifier comprising at least one first circuit block (1, Q1-Q4, Q11-Q12) capable of amplifying a first voltage signal (Vin, V(INP)-V(INN)) in input to the amplifier. The first circuit block (1, Q1-Q4, Q11-Q12) has at least one first terminal coupled to a first supply voltage (Vee) by means of first variable resistor means (RE,2) and at least one second terminal coupled with a second supply voltage (Vcc) by means of at least one resistor (Rc, Rc1, Rc2). The at least one second terminal is coupled to the at least one output terminal of the amplifier (OUT, OUTP-OUTN) and said input voltage signal (Vin, V(INP)-V(INN)) is applied to the at least one further terminal (IN, INP-INN) of the first circuit block. The amplifier comprises a feedback network (RF, RF1, RF2) coupled to the output terminal (OUT, OUTP-OUTN) and to the at least one further terminal (IN, INP-INN) of the first circuit block. The amplifier comprises second circuit means (3) placed between the second supply voltage (Vcc) and the at least one further terminal (IN, INP-INN) of the first circuit block and adapted to compensate the variations in value of said first variable resistor means (RE,2) to ensure a substantially constant input resistance (R in ) of the amplifier.

    3.
    发明专利
    未知

    公开(公告)号：DE60326789D1

    公开(公告)日：2009-05-07

    申请号：DE60326789

    申请日：2003-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALI GIOVANNI ,  PELLERITI ROBERTO ,  TORRISI FELICE

    IPC: H03F3/45

    Abstract: A device for converting a differential signal (Vin1, Vin2) to a single signal (Vout) is described. The device comprises at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and which are arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device. The last comprises a further transistor (Q3) having a first non drivable terminal connected with the output terminal (OUT) of the device, a second non drivable terminal coupled with said second supply voltage (VEE) and the drivable terminal connected with the first terminal of the first passive element (R1). The further transistor (Q3) has such a transconductance gain (gm3) that the product of said transconductance gain (gm3) by said first passive element (R1) is unitary.

    5.
    发明专利
    未知

    公开(公告)号：DE69927004D1

    公开(公告)日：2005-10-06

    申请号：DE69927004

    申请日：1999-06-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALI GIOVANNI ,  PAPARO MARIO ,  PELLERITI ROBERTO

    IPC: G05F1/575

    Abstract: The invention relates to a low-drop type of voltage regulator (1) formed with BiCMOS/CMOS technology and being of the type which comprises: an input terminal (IN), receiving a stable voltage reference (Vrif) and being connected to one input (-) of an operational amplifier (2) through a switch controlled by a power-on enable signal (CE); a supply voltage reference (Vpos) powering the operational amplifier (2); an output transistor (M1) connected to an output (U) of the amplifier (2) to generate a regulated voltage value (Vreg) to be fed back to the amplifier (2) input; a second transistor (M2) connected in series between the output transistor (M1) and the supply voltage reference (Vpos). The regulator of this invention comprises a control circuit portion (7) connected between the control terminal of the second transistor (M2) and the supply voltage reference (Vpos) to prevent the breakdown of the output transistor (M1) from occurring.

    6.
    发明专利
    未知

    公开(公告)号：ITMI20021336A1

    公开(公告)日：2003-12-17

    申请号：ITMI20021336

    申请日：2002-06-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALI GIOVANNI ,  PELLERITI ROBERTO ,  TORRISI FELICE

    IPC: H03F3/45

    Abstract: A device for converting a differential signal (Vin1, Vin2) to a single signal (Vout) is described. The device comprises at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and which are arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device. The last comprises a further transistor (Q3) having a first non drivable terminal connected with the output terminal (OUT) of the device, a second non drivable terminal coupled with said second supply voltage (VEE) and the drivable terminal connected with the first terminal of the first passive element (R1). The further transistor (Q3) has such a transconductance gain (gm3) that the product of said transconductance gain (gm3) by said first passive element (R1) is unitary.

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