中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.024 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE60308346D1

    公开(公告)日：2006-10-26

    申请号：DE60308346

    申请日：2003-07-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  PINNA CARLO

    IPC: H03M1/12 ,  G11C27/02

    Abstract: A boosted sampling circuit easy to realize, the input voltage of which may be greater than the maximum voltage level allowed by prior art circuits or even equal to the supply voltage, is disclosed.This result is attained by connecting the control nodes of the switches M2, M3 and M4 to the input node while the first control phase F1D is active, and by connecting a current terminal of the transistor M2 to a certain voltage for protecting it from breakdowns.A relative method of driving a boosted sampling circuit is also disclosed.

    3.
    发明专利
    未知

    公开(公告)号：DE60015958D1

    公开(公告)日：2004-12-23

    申请号：DE60015958

    申请日：2000-08-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINNA CARLO

    IPC: H03M1/06 ,  H03M1/74

    Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal. In an embodiment the digital to analog conversion circuit able to transform a digital input signal (5) having n bit in an output analog signal (6) comprise: a thermometric decoder (60) having said digital input signal (5) in input and able to produce said signal (SW1-SW7) having a thermometric code with 2 -1 bit in output; a digital to analog converter (21, 31) with modular elements (C1-C7, R1-R7) including 2 -1 controlled switches (I1-I7); a shift register (61) able to receive said digital signal (T1-T7) having 2 -1 bit in an data input and able to produce 2 -1 control signals (SW1-SW7) of said controlled switches (I1-I7) in output; a delay circuit (62) of said of digital input signal (5) having the output connected to a shift input (64) of said shift register (61) and able to produce a delayed digital signal in output as to make said digital signal (T1-T7) having 2 -1 bit shift by a number of bit equal to the value of said delayed digital signal; characterised by further comprising a generator (91) of a digital random number selected in a range of prefixed values and having a prefixed probability of occurrence; an adder node (90) able to receive said random digital number and said delayed digital signal in input whose output is connected to said shift input (64) of said shift register (61).

    5.
    发明专利
    未知

    公开(公告)号：DE60015958T2

    公开(公告)日：2005-12-01

    申请号：DE60015958

    申请日：2000-08-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINNA CARLO

    IPC: H03M1/06 ,  H03M1/74

    Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal. In an embodiment the digital to analog conversion circuit able to transform a digital input signal (5) having n bit in an output analog signal (6) comprise: a thermometric decoder (60) having said digital input signal (5) in input and able to produce said signal (SW1-SW7) having a thermometric code with 2 -1 bit in output; a digital to analog converter (21, 31) with modular elements (C1-C7, R1-R7) including 2 -1 controlled switches (I1-I7); a shift register (61) able to receive said digital signal (T1-T7) having 2 -1 bit in an data input and able to produce 2 -1 control signals (SW1-SW7) of said controlled switches (I1-I7) in output; a delay circuit (62) of said of digital input signal (5) having the output connected to a shift input (64) of said shift register (61) and able to produce a delayed digital signal in output as to make said digital signal (T1-T7) having 2 -1 bit shift by a number of bit equal to the value of said delayed digital signal; characterised by further comprising a generator (91) of a digital random number selected in a range of prefixed values and having a prefixed probability of occurrence; an adder node (90) able to receive said random digital number and said delayed digital signal in input whose output is connected to said shift input (64) of said shift register (61).

Patent Agency Ranking