公开(公告)号：WO2007135694A8

公开(公告)日：2008-12-31

申请号：PCT/IT2006000372

申请日：2006-05-18

Applicant: ST MICROELECTRONICS SRL ,  RONSISVALLE CESARE ,  ENEA VINCENZO

Inventor： RONSISVALLE CESARE ,  ENEA VINCENZO

IPC: H01L29/745 ,  H01L29/74 ,  H01L29/749

CPC classification number: H01L29/7395 ,  H01L29/742 ,  H01L29/7455

Abstract: Described herein is a power device (10) having a first current-conduction terminal (A) , a second current-conduction terminal (K) , a control terminal (G) receiving, in use, a control voltage (VGATE) of the power device (10), and a thyristor device (12) and a first insulated-gate switch device (14) connected in series between the first and the second conduction terminals; the first insulated-gate switch device (14) has a gate terminal connected to the control terminal (G), and the thyristor device (12) has a base terminal (16) . The power device (10) is further provided with: a second insulated-gate switch device (18), connected between the first current-conduction terminal (A) and the base terminal (16) of the thyristor device (12) , and having a respective gate terminal connected to the control terminal (G) ; and a Zener diode (19) , connected between the base terminal (16) of the thyristor device (12) and the second current-conduction terminal (K) so as to enable extraction of current from the base terminal (16) in a given operating condition.

Abstract translation: 这里描述的是具有第一通电端子（A），第二通电端子（K），控制端子（G）的功率器件（10），其在使用中接收功率的控制电压（VGATE） 装置（10）和串联连接在第一和第二导电端子之间的晶闸管装置（12）和第一绝缘栅极开关装置（14） 第一绝缘栅极开关器件（14）具有连接到控制端子（G）的栅极端子，并且晶闸管器件（12）具有基极端子（16）。 功率器件（10）还具有连接在晶闸管器件（12）的第一通电端子（A）和基极端子（16）之间的第二绝缘栅极开关器件（18），并具有 连接到所述控制端子（G）的相应的栅极端子; 和连接在晶闸管器件（12）的基极端子（16）和第二通电端子（K）之间的齐纳二极管（19），以便能够在给定的基极端子（16）中提取电流 操作条件。

公开(公告)号：WO2004102671A8

公开(公告)日：2005-03-17

申请号：PCT/IT0300298

申请日：2003-05-19

Applicant: ST MICROELECTRONICS SRL ,  RONSISVALLE CESARE

Inventor： RONSISVALLE CESARE

IPC: H01L21/332 ,  H01L29/745

CPC classification number: H01L29/66378 ,  H01L29/7455

Abstract: A power device (1) formed by a thyristor (25) and by a MOSFET transistor (26), series-connected between a first and a second current-conduction terminal (A, S). the power device (1) moreover has a control terminal (G) connected to an insulated-gate electrode (20) of the MOSFET transistor (26) and receiving a control voltage for turning on/off the device, and a third current-conduction terminal (B) connected to the thyristor (25) for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reversebias safe-operating area (RBSOA).

Abstract translation: 由晶闸管（25）和串联连接在第一和第二导通端子（A，S）之间的MOSFET晶体管（26）形成的功率器件（1）。 功率器件（1）还具有连接到MOSFET晶体管（26）的绝缘栅电极（20）的控制端子（G），并接收用于接通/关断器件的控制电压和第三电流传导 端子（B）连接到晶闸管（25），用于在关断期间快速提取电荷。 因此，在关闭时，没有当前尾部，并且关闭非常快。 功率器件没有寄生元件，因此具有非常高的反向保护工作区（RBSOA）。

公开(公告)号：IT1320016B1

公开(公告)日：2003-11-12

申请号：ITTO20000319

申请日：2000-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PATTI DAVIDE ,  RONSISVALLE CESARE

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A process for manufacturing deep well junction structures that includes in succession, the steps of: on a first substrate having a first conductivity type and a first doping level, growing an epitaxial layer having the first conductivity type and a second doping level lower than the first doping level; anisotropically etching the epitaxial layer using a mask to form trenches; forming deep conductive regions surrounding the trenches and having a second conductivity type, opposite to the first conductivity type and the second doping level; and filling the trenches. The deep conductive regions are formed by angular ionic implantation and subsequent diffusion of a doping ion species within the epitaxial layer.

公开(公告)号：DE60322828D1

公开(公告)日：2008-09-25

申请号：DE60322828

申请日：2003-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： RONSISVALLE CESARE

IPC: H01L31/078 ,  H03K17/567 ,  H03K17/0416 ,  H03K17/0814

Abstract: An Emitter Switching configuration is described, which comprises at least a bipolar transistor (T1) and a MOS transistor (M1) having a common conduction terminal (E1). The Emitter Switching configuration according to the invention further comprises a Zener diode (DZ3) inserted between a control terminal (B1) of the bipolar transistor (T1) and the common conduction terminal (E1). A monolithic structure is also described, which is effective to implement an Emitter Switching configuration according to the invention.

公开(公告)号：AU2002241256A1

公开(公告)日：2003-09-09

申请号：AU2002241256

申请日：2002-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： RONSISVALLE CESARE

IPC: H01L21/8222 ,  H01L27/07 ,  H01L27/082

公开(公告)号：ITMI20070405A1

公开(公告)日：2008-09-02

申请号：ITMI20070405

申请日：2007-03-01

Applicant: ST MICROELECTRONICS SRL

Inventor： ENEA VINCENZO ,  RONSISVALLE CESARE

公开(公告)号：ITTO20000319A1

公开(公告)日：2001-10-04

申请号：ITTO20000319

申请日：2000-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PATTI DAVIDE ,  RONSISVALLE CESARE

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A process for manufacturing deep well junction structures that includes in succession, the steps of: on a first substrate having a first conductivity type and a first doping level, growing an epitaxial layer having the first conductivity type and a second doping level lower than the first doping level; anisotropically etching the epitaxial layer using a mask to form trenches; forming deep conductive regions surrounding the trenches and having a second conductivity type, opposite to the first conductivity type and the second doping level; and filling the trenches. The deep conductive regions are formed by angular ionic implantation and subsequent diffusion of a doping ion species within the epitaxial layer.

公开(公告)号：AU2003234068A1

公开(公告)日：2004-12-03

申请号：AU2003234068

申请日：2003-05-19

Applicant: ST MICROELECTRONICS SRL

Inventor： RONSISVALLE CESARE

IPC: H01L21/332 ,  H01L29/745

公开(公告)号：ITTO20000319D0

公开(公告)日：2000-04-04

申请号：ITTO20000319

申请日：2000-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PATTI DAVIDE ,  RONSISVALLE CESARE

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A process for manufacturing deep well junction structures that includes in succession, the steps of: on a first substrate having a first conductivity type and a first doping level, growing an epitaxial layer having the first conductivity type and a second doping level lower than the first doping level; anisotropically etching the epitaxial layer using a mask to form trenches; forming deep conductive regions surrounding the trenches and having a second conductivity type, opposite to the first conductivity type and the second doping level; and filling the trenches. The deep conductive regions are formed by angular ionic implantation and subsequent diffusion of a doping ion species within the epitaxial layer.