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公开(公告)号:IT201600130103A1
公开(公告)日:2018-06-22
申请号:IT201600130103
申请日:2016-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor: GENTILI MAURIZIO , SANNINO ROBERTO
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公开(公告)号:ITUA20164622A1
公开(公告)日:2017-12-23
申请号:ITUA20164622
申请日:2016-06-23
Applicant: ST MICROELECTRONICS SRL
Inventor: BERNARDINI ALBERTO , D'ARIA MATTEO , SANNINO ROBERTO
IPC: H04R1/40
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3.
公开(公告)号:IT202000004303A1
公开(公告)日:2021-09-02
申请号:IT202000004303
申请日:2020-03-02
Applicant: ST MICROELECTRONICS SRL
Inventor: D'ARIA MATTEO , SANNINO ROBERTO
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公开(公告)号:ITTO20130968A1
公开(公告)日:2015-05-29
申请号:ITTO20130968
申请日:2013-11-28
Applicant: ST MICROELECTRONICS SRL
Inventor: SANNINO ROBERTO , SPELGATTI LUCA
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公开(公告)号:DE60208012D1
公开(公告)日:2006-01-19
申请号:DE60208012
申请日:2002-07-03
Applicant: ST MICROELECTRONICS SRL
Inventor: PAU DANILO PIETRO , PICCINELLI EMILIANO MARIO ANGE , SANNINO ROBERTO
Abstract: Binary words are converted between a non-encoded format (OP) and a compressed encoded format (V), in which the binary words are, at least in part, represented by encoded bit sequences that are shorter than the respective binary word in the non-encoded format. The shortest encoded bit sequences are selected according to the statistical recurrence of the respective words in the non-encoded format, and associated to the binary words with higher recurrence are encoded bit sequences comprising bit numbers that are accordingly smaller. The correspondence between binary words in non-encoded format and the encoded bit sequences associated to them is established by means of indices of an encoding vocabulary. The conversion process comprises the operations of: arranging the indices according to an ordered sequence; organizing the sequence of indices into groups of vectors (GV); splitting each group of vectors into a given number of vectors (V); and encoding the vectors (V) independently from one another. Alternatively, for each group of vectors, at the end of the encoding process, calculation is carried out - the result being saved in a table, referred to as address-translation table (ATT) - of the starting address on 32 bits of the compressed block or of the differences, expressed in bytes, with respect to the last complete address appearing in said table (ATT).
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公开(公告)号:DE69728369D1
公开(公告)日:2004-05-06
申请号:DE69728369
申请日:1997-01-16
Applicant: ST MICROELECTRONICS SRL
Inventor: SANNINO ROBERTO , BRENNA FILIPPO
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公开(公告)号:DE69734386D1
公开(公告)日:2006-03-02
申请号:DE69734386
申请日:1997-02-06
Applicant: ST MICROELECTRONICS SRL
Inventor: PAU DANILO , BRUNI ROBERTA , SANNINO ROBERTO
IPC: H04N5/92 , G06F17/30 , G06T9/00 , G06T9/40 , H03M7/30 , H04N1/00 , H04N7/01 , H04N7/26 , H04N7/32 , H04N7/50 , H04N19/94
Abstract: The RAM requisite for temporarily storing a stream of digital data blocks in a coding/decoding system of information transferable by blocks may be significantly reduced by compressing and coding the data by blocks through a tree search vector quantization (TSVQ), storing TSVQ compressed and coded data in the RAM and decoding and decompressing during the subsequent reading of the data stored in the RAM thus reconstituting the stream of digital data blocks.
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公开(公告)号:DE69612946T2
公开(公告)日:2001-09-06
申请号:DE69612946
申请日:1996-03-11
Applicant: ST MICROELECTRONICS SRL
Inventor: PAU DANILO , SANNINO ROBERTO
IPC: H04N7/50
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公开(公告)号:DE69612946D1
公开(公告)日:2001-06-28
申请号:DE69612946
申请日:1996-03-11
Applicant: ST MICROELECTRONICS SRL
Inventor: PAU DANILO , SANNINO ROBERTO
IPC: H04N7/50
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