公开(公告)号：JPH11205122A

公开(公告)日：1999-07-30

申请号：JP31113198

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To combine a voltage shift driving circuit having the functional and constitutional features usable by both high voltage and low voltage and capable of reducing the area of a circuit further with a final output stage for supplying power to a load. SOLUTION: In this high voltage final output stage for electric load driving which is constituted of a pair of the transistors of complementary combination connected between a first reference power source (Vdd) and a second reference power source (Vss) and in which the pair of the transistors are constituted by connecting in series at least one PMOS pull-up transistor (MP1) to an NMOS pull-down transistor (MN), an additional PMOS transistor (MP2) is connected in parallel to the PMOS pull-up transistor (MP1) and its body terminal is made to be in common with the PMOS pull-up transistor (MP1).

公开(公告)号：JPH11234118A

公开(公告)日：1999-08-27

申请号：JP31113098

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To provide an electronic level shift circuit for driving a high voltage output stage. SOLUTION: An output stage 2 is provided with a complementary pair of transistors I36 and I32 including at least one PMOS pull-up transistor I32 connected between a first reference voltage source Vdd and a second reference voltage source Vss and serially connected to an NMOS pull-down transistor I36. An additional transistor I34 is parallelly connected to the pull-up transistor I32 and a driving circuit 1 is provided with a first output terminal A connected to the control terminal of the pull-up transistor I32 and a second output terminal B connected to the control terminal of the additional transistor I34.

公开(公告)号：DE69727918D1

公开(公告)日：2004-04-08

申请号：DE69727918

申请日：1997-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCIAN ENRICO ,  MARTIGNONI FABRIZIO ,  DEPETRO RICCARDO

IPC: G11C11/413 ,  G05F3/20 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K17/10

Abstract: The invention relates to a method, and related circuit, for preventing the triggering of a parasitic transistor in an output stage (2) of an electronic circuit, said stage (2) comprising a transistor pair (M1,M2) with at least one transistor (M2) of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor (3) having a terminal connected to said body terminal, characterized in that it comprises the steps of: providing a capacitor (C1) connected between the body and source terminals of the PMOS transistor; using a control circuit (5) to suppress the body effect of the pull-up PMOS transistor.

公开(公告)号：DE69731089D1

公开(公告)日：2004-11-11

申请号：DE69731089

申请日：1997-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H03F1/00

公开(公告)号：DE69731088D1

公开(公告)日：2004-11-11

申请号：DE69731088

申请日：1997-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H03F1/00

Abstract: The invention relates to a high-voltage final output stage (1) for driving an electric load, of the type which comprises a complementary pair (3) of transistors connected between first (Vdd) and second (Vss) supply voltage references, and at least one PMOS pull-up transistor (MP1) connected in series with an NMOS pull-down transistor (MN). The stage (1) comprises an additional PMOS transistor (MP2) connected in parallel with the pull-up transistor (MP1) and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors (MP1,MP2) are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor (MP2) is a thick oxide PMOS power transistor.