公开(公告)号：JPH11205122A

公开(公告)日：1999-07-30

申请号：JP31113198

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To combine a voltage shift driving circuit having the functional and constitutional features usable by both high voltage and low voltage and capable of reducing the area of a circuit further with a final output stage for supplying power to a load. SOLUTION: In this high voltage final output stage for electric load driving which is constituted of a pair of the transistors of complementary combination connected between a first reference power source (Vdd) and a second reference power source (Vss) and in which the pair of the transistors are constituted by connecting in series at least one PMOS pull-up transistor (MP1) to an NMOS pull-down transistor (MN), an additional PMOS transistor (MP2) is connected in parallel to the PMOS pull-up transistor (MP1) and its body terminal is made to be in common with the PMOS pull-up transistor (MP1).

公开(公告)号：JPH11234118A

公开(公告)日：1999-08-27

申请号：JP31113098

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To provide an electronic level shift circuit for driving a high voltage output stage. SOLUTION: An output stage 2 is provided with a complementary pair of transistors I36 and I32 including at least one PMOS pull-up transistor I32 connected between a first reference voltage source Vdd and a second reference voltage source Vss and serially connected to an NMOS pull-down transistor I36. An additional transistor I34 is parallelly connected to the pull-up transistor I32 and a driving circuit 1 is provided with a first output terminal A connected to the control terminal of the pull-up transistor I32 and a second output terminal B connected to the control terminal of the additional transistor I34.

公开(公告)号：JPH0846069A

公开(公告)日：1996-02-16

申请号：JP7625895

申请日：1995-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866

Abstract: PURPOSE: To reduce the dependency on the process parameters of the concentration and/or depth of a buried region, by allowing a second impurity addition stage to have a first sub-step for performing implantation with a low energy and a second sub-step for performing implantation by a low amount of addition and a high energy. CONSTITUTION: When a semiconductor device with a buried junction is manufactured, the impurity in a first format (arsenic) and a second formal (boron) is successively introduced into a silicon chip by the first and second impurity addition stages. An introduced impurity is diffused by a high-temperature treatment, thus forming first and second regions 32 and 33. The amount of impurity to be added and an implantation energy are at a level so that the conduction format (N) of the first region 32 cannot be canceled or inverted, and a concentration at the second region 33 essentially depends on only a second implantation.

公开(公告)号：WO2005104223A8

公开(公告)日：2006-11-23

申请号：PCT/EP2005051694

申请日：2005-04-18

Applicant: ST MICROELECTRONICS SRL ,  PONZA ANNA ,  DEPETRO RICCARDO ,  MONTANINI PIETRO

Inventor： PONZA ANNA ,  DEPETRO RICCARDO ,  MONTANINI PIETRO

IPC: H01L21/78

CPC classification number: H01L21/78

Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer (5') partially suspended above a semiconductor substrate (2) and constrained to the substrate (2) by temporary anchorages (10, 15'); dividing the layer (5') into a plurality of portions (13) laterally separated from one another; and removing the temporary anchorages (10, 15'; 38), in order to free the portions (13).

Abstract translation: 用于制造半导体芯片中的集成器件的方法设想：形成半导体衬底（2）部分悬置并通过临时固定（10,15'）约束到衬底（2）的半导体层（5'）; 将层（5'）分成彼此横向分离的多个部分（13）; 以及移除所述临时锚固件（10,15'; 38），以便释放所述部分（13）。

公开(公告)号：DE60131650D1

公开(公告)日：2008-01-10

申请号：DE60131650

申请日：2001-09-20

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MANZINI STEFANO

IPC: H01L29/94 ,  H01L29/417

Abstract: High-Q, variable capacitance capacitor (20, 20'), comprising a pocket (22) of semiconductor material; a field insulating layer (23), covering the pocket; an opening (24) in the field insulating layer, delimiting a first active area (24); an access region (25) formed in the active area and extending at a distance from a first edge (24a) of the active area and adjacent to a second edge (24b) of the active area. A portion (26) of the pocket (22) is comprised between the access region (15) and the first edge (24a) and forms a first armature; an insulating region (30) extends above the portion (26) of said body, and a polysilicon region (31) extends above the insulating region (30) and forms a second armature. A portion of the polysilicon region extends above the field insulating layer (23), parallel to the access region (25); a plurality of contacts (32) are formed at a mutual distance along the portion of the polysilicon region (31) extending above the field insulating layer (23).

公开(公告)号：DE69727918D1

公开(公告)日：2004-04-08

申请号：DE69727918

申请日：1997-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCIAN ENRICO ,  MARTIGNONI FABRIZIO ,  DEPETRO RICCARDO

IPC: G11C11/413 ,  G05F3/20 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K17/10

Abstract: The invention relates to a method, and related circuit, for preventing the triggering of a parasitic transistor in an output stage (2) of an electronic circuit, said stage (2) comprising a transistor pair (M1,M2) with at least one transistor (M2) of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor (3) having a terminal connected to said body terminal, characterized in that it comprises the steps of: providing a capacitor (C1) connected between the body and source terminals of the PMOS transistor; using a control circuit (5) to suppress the body effect of the pull-up PMOS transistor.

公开(公告)号：ITVI20110247A1

公开(公告)日：2013-03-16

申请号：ITVI20110247

申请日：2011-09-15

Applicant: ST MICROELECTRONICS SRL

Inventor： BELLOMO IGNAZIO SALVATORE ,  DEPETRO RICCARDO ,  NOVELLI ALDO VITTORIO

公开(公告)号：DE60131650T2

公开(公告)日：2008-10-30

申请号：DE60131650

申请日：2001-09-20

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MANZINI STEFANO

IPC: H01L29/94 ,  H01L29/417

Abstract: High-Q, variable capacitance capacitor (20, 20'), comprising a pocket (22) of semiconductor material; a field insulating layer (23), covering the pocket; an opening (24) in the field insulating layer, delimiting a first active area (24); an access region (25) formed in the active area and extending at a distance from a first edge (24a) of the active area and adjacent to a second edge (24b) of the active area. A portion (26) of the pocket (22) is comprised between the access region (15) and the first edge (24a) and forms a first armature; an insulating region (30) extends above the portion (26) of said body, and a polysilicon region (31) extends above the insulating region (30) and forms a second armature. A portion of the polysilicon region extends above the field insulating layer (23), parallel to the access region (25); a plurality of contacts (32) are formed at a mutual distance along the portion of the polysilicon region (31) extending above the field insulating layer (23).

公开(公告)号：DE69415500D1

公开(公告)日：1999-02-04

申请号：DE69415500

申请日：1994-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866 ,  H01L21/82

Abstract: A method is disclosed for forming a first region (32) with conductivity of a first type (N) and second, buried region (30) with conductivity of a second type (P) which forms a junction with the first region (32). By first and second doping steps, impurities of a first (As) and a second (B) type are successively introduced into a silicon chip. A high-temperature treatment causes the impurities thus introduced to diffuse and form said first (32) and second (30) regions. In order to provide a buried region whose concentration and/or depth are little dependent on process parameters, the second doping step comprises a first sub-step of low dosage and high energy implantation, and a second sub-step of low dosage and high energy implantation. The dosages and energies are such that they will not compensate or reverse the type of conductivity of the first region (32), and such that the concentration in the second region (30) will be substantially due to the second implantation step only. This process is compatible with a CMOS-process. The buried junction can be used for a Zener diode, a vertical bipolar transistor or a JFET.

公开(公告)号：DE60035595D1

公开(公告)日：2007-08-30

申请号：DE60035595

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO

IPC: H01L27/08 ,  H01L21/02

Abstract: An inductive structure (1) integrated in a semiconductor substrate (2), comprising at least a conductive element (3) insulated from the substrate (2), comprising an insulating structure (4), which is formed inside said semiconductor substrate (2) and built close to said conductor element (3), so that the resistance of said substrate (2) is increased and the parasitic currents induced by the conductor element (3) in the substrate (2) are decreased.