公开(公告)号：ITVA990037D0

公开(公告)日：1999-12-21

申请号：ITVA990037

申请日：1999-12-21

Applicant: ST MICROELECTRONICS SRL

Inventor： SOLIMENE RAFFAELE

IPC: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/32

Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected.

公开(公告)号：ITVA20000027D0

公开(公告)日：2000-08-10

申请号：ITVA20000027

申请日：2000-08-10

Applicant: ST MICROELECTRONICS SRL

Inventor： SOLIMENE RAFFAELE ,  GENNA GIOVANNI

IPC: H03K19/0185

Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.

公开(公告)号：IT1313403B1

公开(公告)日：2002-07-23

申请号：ITVA990037

申请日：1999-12-21

Applicant: ST MICROELECTRONICS SRL

Inventor： SOLIMENE RAFFAELE

IPC: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/32

Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected.

公开(公告)号：ITVA990037A1

公开(公告)日：2001-06-21

申请号：ITVA990037

申请日：1999-12-21

Applicant: ST MICROELECTRONICS SRL

Inventor： SOLIMENE RAFFAELE

IPC: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/32

Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected.

公开(公告)号：IT1319820B1

公开(公告)日：2003-11-03

申请号：ITTO20000088

申请日：2000-01-28

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  SOLIMENE RAFFAELE

IPC: H03K17/22

公开(公告)号：ITVA20000027A1

公开(公告)日：2002-02-11

申请号：ITVA20000027

申请日：2000-08-10

Applicant: ST MICROELECTRONICS SRL

Inventor： SOLIMENE RAFFAELE ,  GENNA GIOVANNI

IPC: H03K19/0185

公开(公告)号：ITTO20000088A1

公开(公告)日：2001-07-28

申请号：ITTO20000088

申请日：2000-01-28

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  SOLIMENE RAFFAELE

IPC: H03K17/22

Abstract: A power-on reset circuit connected to a supply line feeding a supply voltage, the circuit including an output terminal supplying a power-on reset signal; a divider connected between the supply line (36) and ground and having an intermediate node supplying a division voltage correlated to the supply voltage; an inverter having an input connected to the intermediate node and an output connected to the output terminal and supplying a reset logic signal; and a deactivation branch coupled to the supply line and the intermediate node. The deactivation branch preventing switching of the power-on reset signal on the output terminal when the supply voltage is higher than a deactivation voltage.